EP2S130F1508C5N Altera, EP2S130F1508C5N Datasheet - Page 204
![IC STRATIX II FPGA 130K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S130F1508C5N
Manufacturer Part Number
EP2S130F1508C5N
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1508C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1871
EP2S130F1508C5N
EP2S130F1508C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Timing Model
5–68
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
1.8-V HSTL Class II
PCI
PCI-X
1.2-V HSTL
Differential SSTL-2 Class I
(1),
Differential SSTL-2 Class II
(1),
Differential SSTL-18 Class I
(1),
Differential SSTL-18 Class II
(1),
1.8-V Differential HSTL
Class I (1),
1.8-V Differential HSTL
Class II (1),
1.5-V Differential HSTL
Class I (1),
1.5-V Differential HSTL
Class II (1),
HyperTransport technology
(4)
LVPECL
LVDS
LVDS
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
(3)
(3)
(3)
(3)
(1)
Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
1.2-V HSTL is only supported on column I/O pins.
Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
These numbers apply to dedicated clock pins in the top and bottom I/O banks.
Input I/O Standard
(1)
(5)
(6)
Table
(1)
(3)
(3)
(3)
(3)
(2)
5–77:
Column I/O Pins (MHz)
500
500
500
280
500
500
500
500
500
500
500
500
-3
-
-
-
-
500
500
500
500
500
500
500
500
500
500
500
-4
-
-
-
-
-
500
450
450
500
500
500
500
500
500
500
500
-5
-
-
-
-
-
500
520
520
-3
Row I/O Pins (MHz)
-
-
-
-
-
-
-
-
-
-
-
-
-
500
520
520
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
500
420
420
-5
-
-
-
-
-
-
-
-
-
-
-
-
-
Dedicated Clock Inputs
500
500
500
280
500
500
500
500
500
500
500
500
717
450
717
450
-3
Altera Corporation
(MHz)
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
-4
-
April 2011
500
400
400
500
500
500
500
500
500
500
500
640
400
640
400
-5
-
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