EP2S130F1508C5N Altera, EP2S130F1508C5N Datasheet - Page 97
![IC STRATIX II FPGA 130K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S130F1508C5N
Manufacturer Part Number
EP2S130F1508C5N
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1508C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1871
EP2S130F1508C5N
EP2S130F1508C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
May 2007
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
V
support the voltage-referenced standards (such as SSTL-2). The PLL
banks utilize the adjacent VREF group when voltage-referenced
standards are implemented. For example, if an SSTL input is
implemented in PLL bank 10, the voltage level at VREFB7 is the reference
voltage level for the SSTL input.
I/O pins that reside in PLL banks 9 through 12 are powered by the
VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The EP2S60F484,
EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not
support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are
powered by the VCCIO3 pin, and any I/O pins that reside in bank 12 are
powered by the VCCIO8 pin.
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one V
example, when V
3.3-V PCI for inputs and outputs.
On-Chip Termination
Stratix II devices provide differential (for the LVDS or HyperTransport
technology I/O standard), series, and parallel on-chip termination to
reduce reflections and maintain signal integrity. On-chip termination
simplifies board design by minimizing the number of external
termination resistors required. Termination can be placed inside the
package, eliminating small stubs that can still lead to reflections.
Stratix II devices provide four types of termination:
■
■
■
■
CCIO
Differential termination (R
Series termination (R
Series termination (R
Parallel termination (R
level independently. Each bank also has dedicated VREF pins to
CCIO
is 3.3 V, a bank can support LVTTL, LVCMOS, and
S
S
) without calibration
) with calibration
T
) with calibration
D
)
Stratix II Device Handbook, Volume 1
REF
Stratix II Architecture
voltage level. For
CCIO
2–89
for
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