EP2S130F1508C5N Altera, EP2S130F1508C5N Datasheet - Page 52
![IC STRATIX II FPGA 130K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S130F1508C5N
Manufacturer Part Number
EP2S130F1508C5N
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1508C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1871
EP2S130F1508C5N
EP2S130F1508C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Digital Signal Processing Block
2–44
Stratix II Device Handbook, Volume 1
Multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–6. Multiplier Size & Configurations per DSP Block
DSP Block Mode
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
■
■
■
■
Table 2–6
block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions. The DSP blocks also support mixed modes
and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiply-
accumulator mode, while the other half of the DSP block implements four
9 × 9-bit multipliers in simple multiplier mode.
DSP Block Interface
Stratix II device DSP block input registers can generate a shift register that
can cascade down in the same DSP block column. Dedicated connections
between DSP blocks provide fast connections between the shift register
inputs to cascade the shift register chains. You can cascade registers
within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than
four taps, with additional adder stages implemented in ALMs. If the DSP
block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift
register chain out of the block to cascade multiple columns of DSP blocks.
Four two-multiplier adder
Two four-multiplier adder
Eight multipliers with
eight product outputs
(two 9 × 9 complex
multiply)
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
shows the different number of multipliers possible in each DSP
9 × 9
-
Four multipliers with four
product outputs
Two 52-bit multiply-
accumulate blocks
Two two-multiplier adder
(one 18 × 18 complex
multiply)
One four-multiplier adder
18 × 18
One multiplier with one
product output
Altera Corporation
36 × 36
-
-
-
May 2007
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