EP2S180F1508C3 Altera, EP2S180F1508C3 Datasheet - Page 23
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EP2S180F1508C3
Manufacturer Part Number
EP2S180F1508C3
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1508C3
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
1170
Frequency (max)
778.82MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2164
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1508C3
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA
Quantity:
624
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
May 2007
Figure 2–11. ALM in Arithmetic Mode
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in
equation for this example is:
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
datae0
datae1
dataf0
dataf1
datab
dataa
datad
datac
R = (X < Y) ? Y : X
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_out
carry_in
Stratix II Device Handbook, Volume 1
adder0
adder1
D
D
reg0
reg1
Figure
Q
Q
Stratix II Architecture
2–12. The
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–15