EP2S180F1508C3 Altera, EP2S180F1508C3 Datasheet - Page 32
![IC STRATIX II FPGA 180K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S180F1508C3
Manufacturer Part Number
EP2S180F1508C3
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1508C3
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
1170
Frequency (max)
778.82MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2164
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1508C3
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA
Quantity:
624
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MultiTrack Interconnect
2–24
Stratix II Device Handbook, Volume 1
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect. These column resources include:
■
■
■
■
■
Stratix II devices include an enhanced interconnect structure in LABs for
routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB
for fast shift registers. These ALM to ALM connections bypass the local
interconnect. The Quartus II Compiler automatically takes advantage of
these resources to improve utilization and performance.
shows the shared arithmetic chain, carry chain and register chain
interconnects.
Shared arithmetic chain interconnects in an LAB
Carry chain interconnects in an LAB and from LAB to LAB
Register chain interconnects in an LAB
C4 interconnects traversing a distance of four blocks in up and down
direction
C16 column interconnects for high-speed vertical routing through
the device
Altera Corporation
Figure 2–17
May 2007