EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 62
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 62
“Board Design Considerations” on page 17
“Design and Compilation” on page 28
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Done
Done
N/A
N/A
Use the correct hardware setup when interfacing the Cyclone III device with 3.3/3.0/2.5-V
LVTTL/LVCMOS I/O systems.
Use the Quartus II software to check the restriction on the pin placement.
Minimize the simultaneous switching noise effect on the board with the following methods:
l
l
l
l
l
Connect the device unused pins to the board according to the behavior of the pins.
Terminate the signals according to the I/O standard and signal travel direction.
Perform board-level IBIS or HSPICE simulation.
Minimize the noise on the power planes.
Consider the power-up requirement and I/O behavior of the Cyclone III device during power
up.
Add the correct series resistance to the appropriate configuration signals based on the
configuration scheme used.
Use repeater buffers for the configuration signals when cascading Cyclone III devices in
multi-device configuration.
Ensure that the
Pull the configuration pins high or low through resistors with the recommended values.
Ensure that the devices in a configuration chain are connected properly.
To prevent the signals to the configuration pins from overshooting to more than 4.1 V, use
series resistors and buffers according to the setup.
Do not leave the
Connect the
For AP configuration, select the flash memory from the Intel P30 and P33 families that can
support 40-MHz clock.
Check the pin connection for other pins of the configuration device or flash memory.
Use the
Depending on the on-chip debugging method used, reserve additional resources such as
LE, memory and I/O, and route the JTAG pins out.
Consider the trade-off between schematics or HDL for your design entry based on your
design’s complexity.
Other than the Quartus II software, consider building your design with third-party EDA tools,
SOPC Builder, or IP cores.
If you are using HDL for design entry, use the recommended coding styles.
Distributing simultaneous switching I/O to different I/O banks
Setting unused I/O pins to V
Turning on the slow slew rate feature for the switching pins
Using a lower drive strength for the switching pins
Using the proper termination scheme for the switching pins
areset
MSEL
DCLK
JTAG
,
locked
pins to V
or
pins unconnected.
TCK
CC A
or
signals are clean.
pfdena
C C
or ground directly based on the configuration scheme used.
or ground
control signals as required by your design.
© November 2008 Altera Corporation
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