EP1C20F400I7 Altera, EP1C20F400I7 Datasheet - Page 101

• Manufacturer Part Number: EP1C20F400I7
• Description: IC CYCLONE FPGA 20K LE 400-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C20F400I7

• Number Of Logic Elements/cells: 20060
• Number Of Labs/clbs: 2006
• Total Ram Bits: 294912
• Number Of I /o: 301
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-FBGA
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 20060
• # I/os (max): 301
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 20060
• Ram Bits: 294912
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: FBGA
• No. Of Logic Blocks: 2006
• No. Of Macrocells: 20060
• Family Type: Cyclone
• No. Of Speed Grades: 7
• No. Of I/o's: 301
• Clock Management: PLL
• I/o Supply Voltage: 4.1V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1049

Referenced
Document
Document
Revision History
Altera Corporation
May 2008
May 2008
v1.7
January 2007
v1.6
August 2005
v1.5
February 2005
v1.4
January 2004
v.1.3
October 2003
v.1.2
Table 4–53. Document Revision History
Document
Date and
Version
Minor textual and style changes. Added
section.
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Minor updates.
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Added document revision history.
Added new row for V
Updated R
Added new
Table 4–7
Updated
Updated information in
section.
Updated speed grade information in
Table
Updated LVDS information in
Updated information on Undershoot voltage. Updated Table
4-2.
Updated Table 4-3.
Updated the undershoot voltage from 0.5 V to 2.0 V in Note 3
of Table 4-16.
Updated Table 4-17.
Added extended-temperature grade device information.
Updated Table 4-2.
Updated I
Added clock tree information in Table 4-19.
Finalized timing information for EP1C3 and EP1C12 devices.
Updated timing information in Tables 4-25 through 4-26 and
Tables 4-30 through 4-51.
Updated PLL specifications in Table 4-52.
4–47.
This chapter references the following documents:
■
■
Table 4–53
Note (9)
C C 0
and
CONF
Note (12)
Cyclone Architecture
Operating Requirements for Altera Devices Data Sheet
information in Table 4-3.
Table 4–8
information in
on R
shows the revision history for this chapter.
Changes Made
CCA
on voltage overdrive information to
CONF
“External I/O Delay Parameters”
.
details in
information to
Table
Table 4–3
Table 4–1
chapter in the Cyclone Device Handbook
“Referenced Document”
4–51.
Table 4–46
.
Table
.
4–3.
and
Summary of Changes
Referenced Document
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—
—
Preliminary
4–31