EP1C20F400I7 Altera, EP1C20F400I7 Datasheet - Page 66

• Manufacturer Part Number: EP1C20F400I7
• Description: IC CYCLONE FPGA 20K LE 400-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C20F400I7

• Number Of Logic Elements/cells: 20060
• Number Of Labs/clbs: 2006
• Total Ram Bits: 294912
• Number Of I /o: 301
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-FBGA
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 20060
• # I/os (max): 301
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 20060
• Ram Bits: 294912
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: FBGA
• No. Of Logic Blocks: 2006
• No. Of Macrocells: 20060
• Family Type: Cyclone
• No. Of Speed Grades: 7
• No. Of I/o's: 301
• Clock Management: PLL
• I/o Supply Voltage: 4.1V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1049

Cyclone Device Handbook, Volume 1
3–4
Preliminary
Figure 3–1
Figure 3–1. Cyclone JTAG Waveforms
Table 3–4
devices.
t
t
t
t
t
t
t
t
t
t
t
t
t
Captured
Symbol
J C P
J C H
J C L
J P S U
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
J S C O
J S Z X
J S X Z
Table 3–4. Cyclone JTAG Timing Parameters and Values
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the JTAG timing parameters and values for Cyclone
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
shows the timing requirements for the JTAG signals.
clock period
clock high time
clock low time
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
Min
100
50
50
20
45
20
45
—
—
—
—
—
—
t
JPXZ
Max Unit
25
25
25
35
35
35
—
—
—
—
—
—
—
May 2008
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns