EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 122
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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6–22
Table 6–7. Chapter Revision History (Part 2 of 3)
Cyclone III Device Handbook, Volume 1
May 2008
Date
Version
2.0
Changes include addition of BLVDS information.
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Added an introduction to “I/O Element Features” section.
Updated “Slew Rate Control” section.
Updated “Programmable Delay” section.
Updated Table 6–1 with BLVDS information.
Updated Table 6–2.
Updated “PCI-Clamp Diode” section.
Updated “LVDS Transmitter Programmable Pre-Emphasis” section.
Updated “On-Chip Termination with Calibration” section and added new
Figure 6–9.
Updated Table 6–3 title.
Updated Table 6–4 unit.
Updated “I/O Standards” section and Table 6–5 with BLVDS information and
added (Note 5).
Updated “Differential I/O Standard Termination” section with BLVDS
information.
Updated “I/O Banks” section.
Updated (Note 2) and added (Note 7) and BLVDS information to
Figure 6–15.
Updated (Note 2) and added BLVDS information to Table 6–6.
Added MBGA package information to Table 6–7.
Deleted Table 6-8.
Updated “High-Speed Differential Interfaces” section with BLVDS
information.
Updated “Differential Pad Placement Guidelines” section and added new
Figure 6–16.
Updated “V
Figure 6–17.
Updated Table 6–11.
Added new “DCLK Pad Placement Guidelines” section.
Updated “DC Guidelines” section.
REF
Pad Placement Guidelines” section and added new
Chapter 6: I/O Features in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History
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