EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 67
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2)
© December 2009
PLL4_C0
PLL4_C1
PLL4_C2
PLL4_C3
PLL4_C4
DPCLK0
DPCLK1
DPCLK7
CDPCLK0, or
CDPCLK7 (2),
DPCLK2
CDPCLK1, or
CDPCLK2 (2),
DPCLK5
DPCLK7
DPCLK4
DPCLK6
DPCLK6
CDPCLK5, or
CDPCLK6 (2),
DPCLK3
CDPCLK4, or
CDPCLK3 (2),
DPCLK8
DPCLK11
DPCLK9
DPCLK10
DPCLK5
DPCLK2
DPCLK4
DPCLK3
Notes to
(1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9.
(2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices.
(3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2.
(4) This pin applies only to EP3C5 and EP3C10 devices.
(5) Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin.
GCLK Network Clock
Sources
Table
(4)
(4)
(4)
(2)
(4)
(2)
(4)
(4)
5–1:
(5)
(5)
(5)
(5)
Altera Corporation
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0
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1
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Cyclone III Device Handbook, Volume 1
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5–3
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