EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 86
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–22
Programmable Bandwidth
Phase Shift Implementation
Cyclone III Device Handbook, Volume 1
■
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. Cyclone III device family PLLs provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Phase shift is used to implement a robust solution for clock delays in the Cyclone III
device family. Phase shift is implemented with a combination of the VCO phase
output and the counter starting time. The VCO phase output and counter starting
time are the most accurate methods of inserting delays, because they are purely based
on counter settings, which are independent of process, voltage, and temperature.
You can phase shift the output clocks from the Cyclone III device family PLLs in
either:
■
■
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution.
shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine Resolution Phase Shift
in which f
For example, if f
Φfine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that
depends on reference clock frequency and counter settings.
Φ fine
Disable the system during switchover if the system is not tolerant to frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (pfdena = 0) so the VCO
maintains its last frequency. You can also use the switchover state machine to
switch over to the secondary clock. Upon enabling the PFD, output clock enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clock or clocks.
Fine resolution using VCO phase taps, or
Coarse resolution using counter starting time
=
T
-----------
VCO
8
REF
=
is the input reference clock frequency.
------------- -
8f
REF
1
VCO
is 100 MHz, N = 1, and M = 8, then f
=
---------------- - -
8Mf
N
R EF
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
VCO
© December 2009 Altera Corporation
= 800 MHz, and
Programmable Bandwidth
Equation 5–1