EP20K100EFI324-2X Altera, EP20K100EFI324-2X Datasheet - Page 26
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EP20K100EFI324-2X
Manufacturer Part Number
EP20K100EFI324-2X
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100EFI324-2X
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2091
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APEX 20K Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Note to
(1)
26
APEX 20KE devices have four dedicated clocks.
From
Adjacent
LAB
Figure
Local
Interconnect
13:
65
Dedicated Clocks
Global Signals
Macrocells
APEX 20K macrocells can be configured individually for either sequential
or combinatorial logic operation. The macrocell consists of three
functional blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
software Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset.
4
2 or 4 (1)
Figure 14
9
32
shows the APEX 20K macrocell.
2
2
2
MegaLAB Interconnect
ENA[1..0]
CLK[1..0]
CLRN[1..0]
Macrocell
Inputs (1-16)
16
Altera Corporation
To Row
and Column
Interconnect