EP20K100EFI324-2X Altera, EP20K100EFI324-2X Datasheet - Page 39
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EP20K100EFI324-2X
Manufacturer Part Number
EP20K100EFI324-2X
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100EFI324-2X
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2091
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
Figure 25. APEX 20K Bidirectional I/O Registers
Note to
(1)
or Local Interconnect
The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Row, Column,
Figure
25:
4 Dedicated
Inputs
Clock Inputs
2 Dedicated
2
Peripheral Control
Bus
12
OE[7..0]
VCC
CLK[1..0]
CLK[3..2]
ENA[5..0]
CLRn[1..0]
VCC
Input Pin to Input
Core to Output
Register Delay
VCC
VCC
Register Delay
VCC
VCC
VCC
APEX 20K Programmable Logic Device Family Data Sheet
Chip-Wide
Chip-Wide
Chip-Wide Reset
Input Pin to
Reset
Reset
Core Delay
Note (1)
Output Enable
Output Register
Chip-Wide
Input Register
OE Register
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
Q
Q
Q
Open-Drain
Slew-Rate
Output
Control
Output Register
t
CO
Delay
VCCIO
Optional
PCI Clamp
39