EP1S20F484C7 Altera, EP1S20F484C7 Datasheet - Page 125
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C7
Manufacturer Part Number
EP1S20F484C7
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F484C7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
361
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1101
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C7
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S20F484C7N
Manufacturer:
ALTERA
Quantity:
351
Altera Corporation
July 2005
and/or output enable registers. A programmable delay exists to increase
the t
Table 2–24
The IOE registers in Stratix devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power-up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally a
synchronous reset signal is available for the IOE registers.
Double-Data Rate I/O Pins
Stratix devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 2–65
the DDR input timing diagram.
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Output enable register t
Output t
Output clock enable delay
Input clock enable delay
Logic array to output register delay
Output enable clock enable delay
Table 2–24. Stratix Programmable Delay Chain
ZX
Programmable Delays
delay to the output pin, which is required for ZBT interfaces.
ZX
delay
shows the programmable delays for Stratix devices.
shows an IOE configured for DDR input.
CO
delay
Decrease input delay to internal cells
Decrease input delay to input register
Increase delay to output pin
Increase delay to output enable pin
Increase t
Increase output clock enable delay
Increase input clock enable delay
Decrease input delay to output register
Increase output enable clock enable delay
Stratix Device Handbook, Volume 1
Quartus II Logic Option
ZX
delay to output pin
Figure 2–66
Stratix Architecture
shows
2–111