EP1S20F484C7 Altera, EP1S20F484C7 Datasheet - Page 62

• Manufacturer Part Number: EP1S20F484C7
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 361
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1101

TriMatrix Memory
Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–48
Stratix Device Handbook, Volume 1
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
wren
rden
Figure
8 LAB Row
Clocks
8
2–26:
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Notes
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
(1),
512 ´ 8
(2)
D
ENA
Q
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July 2005