EP1S20F484C7 Altera, EP1S20F484C7 Datasheet - Page 154
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C7
Manufacturer Part Number
EP1S20F484C7
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F484C7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
361
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1101
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C7
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S20F484C7N
Manufacturer:
ALTERA
Quantity:
351
Power Sequencing & Hot Socketing
Power
Sequencing &
Hot Socketing
2–140
Stratix Device Handbook, Volume 1
The transmitter external clock output is transmitted on a data channel.
The txclk pin for each bank is located in between data transmitter pins.
For ×1 clocks (e.g., 622 Mbps, 622 MHz), the high-speed PLL clock
bypasses the SERDES to drive the output pins. For half-rate clocks (e.g.,
622 Mbps, 311 MHz) or any other even-numbered factor such as 1/4, 1/7,
1/8, or 1/10, the SERDES automatically generates the clock in the
Quartus II software.
For systems that require more than four or eight high-speed differential
I/O clock domains, a SERDES bypass implementation is possible using
IOEs.
Byte Alignment
For high-speed source synchronous interfaces such as POS-PHY 4, XSBI,
RapidIO, and HyperTransport technology, the source synchronous clock
rate is not a byte- or SERDES-rate multiple of the data rate. Byte
alignment is necessary for these protocols since the source synchronous
clock does not provide a byte or word boundary since the clock is one half
the data rate, not one eighth. The Stratix device’s high-speed differential
I/O circuitry provides dedicated data realignment circuitry for user-
controlled byte boundary shifting. This simplifies designs while saving
LE resources. An input signal to each fast PLL can stall deserializer
parallel data outputs by one bit period. You can use an LE-based state
machine to signal the shift of receiver byte boundaries until a specified
pattern is detected to indicate byte alignment.
Because Stratix devices can be used in a mixed-voltage environment, they
have been designed specifically to tolerate any possible power-up
sequence. Therefore, the VCCIO and VCCINT power supplies may be
powered in any order.
Although you can power up or down the VCCIO and VCCINT power
supplies in any sequence, you should not power down any I/O banks
that contain configuration pins while leaving other I/O banks powered
on. For power up and power down, all supplies (VCCINT and all VCCIO
power planes) must be powered up and down within 100 ms of each
other. This prevents I/O pins from driving out.
Signals can be driven into Stratix devices before and during power up
without damaging the device. In addition, Stratix devices do not drive
out during power up. Once operating conditions are reached and the
device is configured, Stratix devices operate as specified by the user. For
more information, see Hot Socketing in the Selectable I/O Standards in
Stratix & Stratix GX Devices chapter in the Stratix Device Handbook,
Volume 2.
Altera Corporation
July 2005