EP3C120F780C7N Altera, EP3C120F780C7N Datasheet - Page 30

• Manufacturer Part Number: EP3C120F780C7N
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C7N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2394; 544-2532; 544-2532; EP3C120F780C7NES

1–20
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications
Cyclone III Device Handbook, Volume 2
t
t
t
Notes to
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
(2) t
f
clock
frequency)
Device
operation in
Mbps
t
TCCS
Output jitter
(peak to
peak)
t
t
t
Notes to
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
(3) t
RISE
FALL
LOCK
HSC LK
DUTY
RISE
FALL
LOCK
Symbol
Symbol
(2)
(3)
at the output pin of all I/O banks.
LOC K
LOC K
(input
Table
Table
is the time required for the PLL to lock from the end of device configuration.
is the time required for the PLL to lock from the end of device configuration.
1–27:
1–28:
20 – 80%,
C
20 – 80%,
C
20 – 80%,
C
20 – 80%,
C
LOAD
LOAD
LOAD
LOAD
Modes
= 5 pF
= 5 pF
Modes
= 5 pF
= 5 pF
—
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
500
500
Typ
C6
—
C6
Typ
500
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
Max
200
200
200
200
200
400
400
400
400
400
400
400
200
500
55
—
—
—
—
1
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
Min
—
—
—
C7, I7
C7, I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
Typ
—
155.5
155.5
155.5
155.5
155.5
(Note 1)
Max
311
311
311
311
311
311
311
200
500
55
—
—
1
Max
—
—
1
,
(2)
Min
Chapter 1: Cyclone III Device Data Sheet
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
(Note 1)
Min
—
—
—
© January 2010 Altera Corporation
C8, A7
C8, A7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
Typ
—
(Part 2 of 2)
Switching Characteristics
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
311
311
200
550
Max
55
—
—
—
—
1
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ms
ms
ps
ps
ps
ps
ps
ps
%