EP3C120F780C7N Altera, EP3C120F780C7N Datasheet - Page 65

• Manufacturer Part Number: EP3C120F780C7N
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C7N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2394; 544-2532; 544-2532; EP3C120F780C7NES

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
© December 2009
Altera Corporation
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter Timing
Specifications
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications
f
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) t
(Part 1 of 2) (Preliminary)
f
frequency)
HSIODR
SW
HSC LK
DUTY
LOCK
HSC LK
(2)
LOC K
Symbol
Symbol
(input clock
(input clock
Table
is the time required for the PLL to lock from the end of device configuration.
2–30:
(Note 1)
Modes
Modes
(Preliminary)
×10
×10
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C7 and I7
C7 and I7
402.5
402.5
402.5
402.5
Max
Max
370
370
370
370
370
740
740
740
740
740
400
320
320
320
320
320
640
640
640
640
640
200
500
55
1
Cyclone III Device Handbook, Volume 2
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
(Note 1)
C8
C8
402.5
402.5
402.5
402.5
Max
Max
320
320
320
320
320
640
640
640
640
640
400
275
275
275
275
275
550
550
550
550
550
200
550
55
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
MHz
MHz
MHz
MHz
MHz
MHz
ms
ps
ps
%
%
2–21