EP20K400EFC672-2X Altera, EP20K400EFC672-2X Datasheet - Page 115

IC APEX 20KE FPGA 400K 672-FBGA

EP20K400EFC672-2X

Manufacturer Part Number
EP20K400EFC672-2X
Description
IC APEX 20KE FPGA 400K 672-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K400EFC672-2X

Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
APEX 20K
Number Of Usable Gates
400000
Number Of Logic Blocks/elements
16640
# Registers
104
# I/os (max)
488
Frequency (max)
223MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
16640
Ram Bits
212992
Device System Gates
1052000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2095

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Altera Corporation
Revision
History
The information contained in the APEX 20K Programmable Logic Device
Family Data Sheet version 5.1 supersedes information published in
previous versions.
Version 5.1
APEX 20K Programmable Logic Device Family Data Sheet version 5.1
contains the following changes:
Version 5.0
APEX 20K Programmable Logic Device Family Data Sheet version 5.0
contains the following changes:
Version 4.3
APEX 20K Programmable Logic Device Family Data Sheet version 4.3
contains the following changes:
Version 4.2
APEX 20K Programmable Logic Device Family Data Sheet version 4.2
contains the following changes:
In version 5.0, the VI input voltage spec was updated in Table 28 on
page 63.
In version 5.0,
Added
Updated
tables because all APEX 20K devices are now 5.0-V tolerant.
Updated conditions in
Updated data for t
Updated
Updated
Updated notes to
Updated
Updated
Note (2)
Tables 23
Figure
Note (2)
Figure
Note (1)
APEX 20K Programmable Logic Device Family Data Sheet
Note (5)
to
20.
29.
to
to
Tables 27
Figure 21 on page
ESBDATAH
through 26. Removed 2.5-V operating condition
Table
Figure
to
Tables
Tables 27
13.
29.
through 30.
parameter.
33,
38
through
and 39.
33.
30
was revised.
115

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