EP1S40F1020C6 Altera, EP1S40F1020C6 Datasheet - Page 203

no-image

EP1S40F1020C6

Manufacturer Part Number
EP1S40F1020C6
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40F1020C6

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1425
EP1S40SF1020C6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40F1020C6
Manufacturer:
ALTERA
Quantity:
784
Part Number:
EP1S40F1020C6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S40F1020C6
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C6
Manufacturer:
ALTERA
Quantity:
180
Part Number:
EP1S40F1020C6ES
Manufacturer:
ALTERA
0
Company:
Part Number:
EP1S40F1020C6ES
Quantity:
6
Part Number:
EP1S40F1020C6L
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C6N
Manufacturer:
Altera
Quantity:
10 000
Altera Corporation
January 2006
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
IOE pin timing. All registers are within the IOE.
Figure 4–4. External Timing in Stratix Devices
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
24-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in
Dedicated
Clock
Figure 4–4
shows the pin-to-pin timing model for bidirectional
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–103
Bidirectional
Pin
through 4–108.
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
4–33

Related parts for EP1S40F1020C6