EP1S40F1020C6 Altera, EP1S40F1020C6 Datasheet - Page 269

• Manufacturer Part Number: EP1S40F1020C6
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1425; EP1S40SF1020C6

Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Exact, user-controllable value depends on the PLL settings.
(11) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
t
t
f
% spread
t
LSKEW
SKEW
SS
ARESET
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 3 of 3)
Symbol
The minimum input clock frequency to the PFD (f
Use this equation (f
to determine the allowed PLL settings.
See
t
This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
Actual jitter performance may vary based on the system configuration.
Total required time to reconfigure and lock is equal to t
changed, then t
When using the spread-spectrum feature, the minimum VCO frequency is 500 MHz. The maximum VCO
frequency is determined by the speed grade selected.
Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
FCOMP
“Maximum Input & Output Clock Rates” on page
Tables 4–127
can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
Clock skew between two external
clock outputs driven by the same
counter
Clock skew between two external
clock outputs driven by the different
counters with the same settings
Spread spectrum modulation
frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
DLOCK
through 4–130:
OUT
is equal to 0.
= f
Parameter
I N
* ml(n × post-scale counter)) in conjunction with the specified f
(10)
areset
IN
/N) must be at least 3 MHz for Stratix device enhanced PLLs.
Min
0.5
30
10
4–76.
DLOCK
±50
±75
Typ
+ t
CONFIG
. If only post-scale counters and delays are
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Max
150
0.6
I N P F D
and f
V C O
ranges
Unit
kHz
ps
ps
ns
%
4–99