EP1S40F1020C6 Altera, EP1S40F1020C6 Datasheet - Page 267

• Manufacturer Part Number: EP1S40F1020C6
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1425; EP1S40SF1020C6

Altera Corporation
January 2006
t
t
t
t
t
t
t
f
t
t
f
% spread
t
f
f
f
f
t
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
LSKEW
SKEW
SS
ARESET
IN
INPFD
INDUTY
EINDUTY
INJITTER
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3)
Symbol
Symbol
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the
scan chains for PLLs 5 and 6
Time required to reconfigure the
scan chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
(11)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Clock skew between two external
clock outputs driven by the same
counter
Clock skew between two external
clock outputs driven by the different
counters with the same settings
Spread spectrum modulation
frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
Input clock frequency
Input frequency to PFD
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
Parameter
Parameter
(10)
(5)
(11)
areset
(7)
(1),
Min
Min
300
0.5
(9)
40
40
45
10
30
10
3
3
(2)
Typ
±50
±75
Typ
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
289/f
193/f
±200
600
Max
480
420
Max
100
400
150
60
60
0.6
55
22
SCANCLK
SCANCLK
(8)
(3)
MHz
MHz
Unit
ps or
MHz
MHz
Unit
mUI
kHz
ps
%
%
ps
ps
ns
μs
μs
%
%
4–97