EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 149
EP2SGX130GF1508I4N
Manufacturer Part Number
EP2SGX130GF1508I4N
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX130GF1508I4N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2175
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Sunon
Quantity:
1 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–90. Fast PLL and Channel Layout in the EP2SGX30C/D and EP2SGX60C/D Devices
Note to
(1)
Altera Corporation
October 2007
See
Figure
Table 2–38
2–90:
4
for the number of channels each device supports.
2
2
4
4
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols because the source synchronous clock does
not provide a byte or word boundary since the clock is one half the data
rate, not one eighth. The Stratix II GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row.
channel layout in the EP2SGX30C/D and EP2SGX60C/D devices.
Figure 2–91
EP2SGX90E/F, and EP2SGX130G devices.
PLL 1
PLL 2
Fast
Fast
LVDS
LVDS
Clock
Clock
shows the fast PLL and channel layout in EP2SGX60E,
Clock
Clock
DPA
DPA
Quadrant
Quadrant
Stratix II GX Device Handbook, Volume 1
Figure 2–90
shows the fast PLL and
Quadrant
Quadrant
Stratix II GX Architecture
Note (1)
2–141
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