EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 95
EP2SGX130GF1508I4N
Manufacturer Part Number
EP2SGX130GF1508I4N
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX130GF1508I4N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2175
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Sunon
Quantity:
1 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–60. DSP Block Interface to Interconnect
Altera Corporation
October 2007
C4 Interconnect
LAB
18
f
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in
Refer to the
Stratix II GX Device Handbook for more information on DSP blocks.
Row Interface
36
12
Block
DSP Blocks in Stratix II GX Devices
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
Stratix II GX Device Handbook, Volume 1
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
Table
36
chapter in volume 2 of the
Stratix II GX Architecture
2–23.
Direct Link Interconnect
from Adjacent LAB
LAB
2–87
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