EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 292
EP2SGX130GF1508I4N
Manufacturer Part Number
EP2SGX130GF1508I4N
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX130GF1508I4N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2175
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Sunon
Quantity:
1 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
Table 4–100. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices
Note (1)
Maximum DCD (ps) for
Row DDIO Output I/O
The information in
Standard
Table 4–100
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is 2.5-V SSTL-2 and the DDIO output I/O
standard is SSTL-2 Class= II, the maximum DCD is 60 ps (see
Table
Calculate the DCD as a percentage:
3.3 and
2.5 V
260
210
195
150
255
175
170
155
150
150
180
assumes the input clock has zero DCD.
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
(T/2 – DCD) / T = (3,745 ps/2 – 60 ps) / 3745 ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 60 ps) / 3745 ps = 51.6% (for high
boundary)
TTL/CMOS
4–100). If the clock frequency is 267 MHz, the clock period T is:
Input I/O Standard (No PLL in Clock Path)
1.8 and
1.5 V
380
330
315
265
370
295
290
275
270
270
180
SSTL-2
2.5 V
145
100
140
180
85
85
65
60
55
60
55
SSTL/HSTL
1.8 and
1.5 V
100
180
145
140
85
85
60
55
65
60
50
LVDS
3.3 V
110
120
105
180
65
75
70
75
90
95
90
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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