EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet
EP4SGX290KF40C3N
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EP4SGX290KF40C3N Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www ...
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... All Stratix IV GX (ES and production) devices CCPD ® (PCIe) rate switch controller may not be initialized correctly for the ® II software versions 10.1 SP1 and later. Altera PCIe Gen2 Protocol Link Production Devices for Stratix IV GX Devices Planned Fix — No plan to fix silicon. For a soft-fix solution, refer to “ ...
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... The transceiver channels configured in PCIe mode are NOT affected by this issue. Solution This issue is fixed in the Quartus II software versions 10.1 and later. Altera recommends upgrading to the latest Quartus II software and recompiling your design. For complete details of the solution, refer to the Additionally, software patches are available for the Quartus II software versions 9 ...
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... The actual amount of additional jitter depends on the device switching activity. The EP4SGX180 and EP4SGX230 production ordering codes are not affected. Altera is fixing this issue in the next revision of production devices, which will meet all current jitter specifications. f For further support, file a service request using mysupport ...
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... Reference Clock Pre-Divider Designs that implement the recommended transceiver reset sequence described in the Reset Control and Power Down could potentially see a link failure after coming out of reset. March 2011 Altera Corporation Figure 1 shows the reference clock pre-divider inside CMU/ATX PLL Lock ...
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... Errata Sheet for Stratix IV GX Devices Figure serdes_io cal_blk_clk pll_inclk pll_powerdown[0..0] tx_datain[39..0] pll_powerdown tx_datain[39..0] tx_digitalreset tx_digitalreset[0..0] inst pll_locked_soft_logic clk reset pll_locked_from_altgx inst2 to obtain the module. Production Devices for Stratix IV GX Devices 3. The pll_locked[0..0] tx_clkout[0..0] tx_dataout[0..0] top_tx_dataout pll_locked_to_corelogic March 2011 Altera Corporation ...
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... Alternatively, you can also apply this setting to individual M144K blocks with the Assignment Editor. Global and per instance assignments can be mixed. For example, you can set DCD to On globally, but set it to Off for an instance. You can also only set instance. March 2011 Altera Corporation Page 7 performance ...
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... You must use the ATX PLL (6G) between the two 6.5 transceiver blocks. For more information, refer to Figure 4. You must use the ATX PLL (6G) adjacent to the transceiver block where the 6.5 channels are located. For more information, refer to Figure 5. March 2011 Altera Corporation ...
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... CEI ATX PLL (6G) — PHY Interface Notes to Table 2: (1) Contact Altera Technical Support for guidance about V (2) The ATX PLL (6G) is not available in C4 and I4 speed grades in Stratix IV GX devices. March 2011 Altera Corporation Supported Data Rates V / CCL_GXB V ...
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... Production Devices for Stratix IV GX Devices CMU1 Channel CMU0 Channel CMU1 Channel CMU0 Channel ATX PLL (6 G) CMU1 Channel CMU0 Channel ATX PLL (6 G) CMU1 Channel CMU0 Channel Basic ×8 Link Placed in the Middle Two Transceiver Blocks of a EP4SGX530NF45 Device March 2011 Altera Corporation ...
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... CMU0 Channel CMU1 Channel CMU0 Channel ATX PLL (6 G) CMU1 Channel CMU0 Channel ATX PLL (6 G) CMU1 Channel CMU0 Channel March 2011 Altera Corporation CMU1 Channel CMU1 Channel CMU0 Channel CMU0 Channel CMU1 Channel CMU1 Channel CMU0 Channel CMU0 Channel ATX PLL (6 G) ...
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... CMU0 Channel ATX PLL (6 G) Production Devices for Stratix IV GX Devices CMU0 Channel ATX PLL (6 G) ATX PLL (6 G) CMU1 Channel CMU0 Channel Basic (PMA Direct) ×17 Link Placed in the Top Three Transceiver Blocks of a EP4SGX530NF45 Device March 2011 Altera Corporation ...
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... Production Devices for Stratix IV GX Devices Figure 7. Placement Restrictions in Basic (PMA Direct) ×N (N=24) Mode using ATX PLL (6G) March 2011 Altera Corporation ATX PLL (6 G) ATX PLL (6 G) Basic (PMA Direct) ×24 Link in a EP4SGX530NF45 Device Page 13 Errata Sheet for Stratix IV GX Devices ...
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... Supply and Data Rate Restrictions in Your Configured ALTGX Functional Mode Is the Desired Data Rate No Table 2 for Stratix IV GX production devices. Table 2. Production Devices for Stratix IV GX Devices No No Action Required Stratix IV GX Devices Cannot Support This Configuration Table 2. March 2011 Altera Corporation ...
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... For more information about the impact of ×N clock line issue, refer to the Stratix Stratix IV GT Errata sheet section "×8 and ×N Clock Line Timing Issue for Transceivers." March 2011 Altera Corporation Figure 9. Then recompile the project. ...
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... Planned Fix Quartus II 10.1 SP1 and later. Patches are available for the Quartus II software versions 9.1 SP2 and 10.1. Quartus II Software 10.1 and later. Patches are available for the Quartus II software versions 9.1 SP2 and 10.0 SP1. March 2011 Altera Corporation ...
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... Write with Dual-Port Dual-Clock Modes” M144K RAM blocks may not operate correctly in dual-port dual-clock modes. “Automatic Clock Switchover” Automatic clock switchover feature may not operate correctly. March 2011 Altera Corporation Affected Devices No plan to fix silicon. Apply reset workaround in All Stratix IV GX Reconfiguration Issue Between ...
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... Stratix Family Issues Planned Fix Production devices Production devices Refer to Table 1 on page 1 Production devices Production devices Production devices Production devices Production devices Production devices Production devices Production devices For more information, refer to “DPA Misalignment” on page 28. March 2011 Altera Corporation ...
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... The remote system upgrade feature works correctly with all other reconfiguration trigger conditions. This issue is addressed by using the updated ALTREMOTE_UPDATE megafunction and will be available in the Quartus II software version 9.1, or contact Altera Technical Support for the software patch available with the Quartus II software version 9.0 SP2. March 2011 Altera Corporation “ ...
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... T = End of Packet D = Data Packet A = Alignment Character K = Lane Synchronization Character R = Clock Rate Compensation Character Altera provides a soft IP solution and associated documentation, available for download at: www.altera.com/patches/xaui-softip/xaui-softip-fix-reva.zip This soft IP should be integrated into the XAUI receiver data path. This issue is fixed in production devices. Timing Issue with Two Channels in Basic (PMA Direct) Configuration ...
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... This issue only occurs with the error injection block and is fixed in production devices. The CRC Error Detection feature operates correctly as expected, and is not affected by this issue. If you need to use the CRC Error Injection feature with ES devices, contact Altera Technical Support. Higher Power Supply Current During Power-Up for V ...
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... Disabling the CRC Error Detection feature in your design compilation with the Quartus II software will prevent this issue from occurring in ES devices. This issue is fixed in production devices. Errata Sheet for Stratix IV GX Devices Stratix Family Issues March 2011 Altera Corporation ...
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... Gbps. If you require 3 MegaWizard Plug-In Manager. Though the Quartus II software report files continue to indicate 3.0 V connections CCA_L March 2011 Altera Corporation Table 4). Stratix IV GX -2×, -3, and -4 speed grade ES devices do not Power Supply Level (V) 2.5/3.0/3.3 Transceiver high voltage power (left side) 2 ...
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... Library Release Notes and Errata document. 5 Gbps to 6.5 Gbps (-2 speed grade with higher transceiver power ■ supplies and V CCR_L/R CCT_L/R set to 1.2 ± 0.05 V) 600 Mbps to 5 Gbps (-2, -2x, -3, and -4 speed grades) ■ Stratix Family Issues MegaCore IP power supplies must be CCL_GXB_L/Rn March 2011 Altera Corporation ...
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... Gbps (-2, -2x, and -3 speed grades) ■ Contact Altera Technical Support. Use PCIe Gen2 ×4 functional mode using CMU PLL only. 3.125 Gbps to 5.4 Gbps for -2, -2×, and -3 speed grades 5.4 Gbps for -2, -2×, and -3 speed grades. ...
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... I/O pins. The actual amount of additional jitter is application and toggle-rate dependent. High-speed transceiver I/O pins are unaffected and perform to data sheet specifications. Altera has fixed the issue in production devices, which meets all current jitter specifications. If you are using ES devices, you need to account for this additional timing uncertainty in all non-transceiver I/O timing closure budgets ...
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... EP4SGX230 ES device transceiver blocks. Settings with M=16 and M=20 in all ALTGX PLLs are removed from Basic modes and all protocol configurations. These changes resulted in blocking one configuration for Sonet OC-48 (RefCLK = 77.76 MHz). March 2011 Altera Corporation settings by searching under “Nominal INPFD . ...
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... LVDS receivers configured in Soft CDR mode with 0 PPM difference (synchronous interface) are also affected. For applications with flexibility in the choice of training patterns, Altera recommends you choose bit sequences with more data transitions and a non-cyclical pattern similar to a PRBS or K28.5 code sequence. ...
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... MLAB. Revised the first sentence of this section. Updated “×8 and ×N Clock Line Timing Issue for Transceivers”, “M144K Write with ■ Dual-Port Dual-Clock Modes”, and “CRC Error Detection Feature” sections March 2011 Altera Corporation Changes Errata Sheet for Stratix IV GX Devices Page 29 ...
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... Settings for Transceivers” ■ “DPA Misalignment” ■ Errata Sheet for Stratix IV GX Devices Changes Power Supply Levels” CC Setting” INPFD Power Supply” CC Setting” INPFD Supply” CC Document Revision History and V ” CCPD CCA_L/R March 2011 Altera Corporation ...