EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 20

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Page 20
Figure 10. Rate Match FIFO Skew
Errata Sheet for Stratix IV GX Devices
Correct Channel Alignment
XAUI Protocol Purposes
XAUI Protocol Purposes
Skewed Channel 0
XAUI Functional Mode Failure
Timing Issue with Two Channels in Basic (PMA Direct) Configuration
Master Channel for
Master Channel for
f
In XAUI functional mode, the data out of the physical transceiver channel 0’s Rate
Match FIFO may be shifted by one byte with respect to the data of the other three
channels. This causes incorrect idle ordered set conversion, resulting in incorrect
received parallel data. The corrupted received parallel data caused by improper idle
ordered set conversion or rate matcher corruption happens only during initialization
or receiver channel reset (assertion of rx_analogreset or rx_digitalreset).
Figure 10
Altera provides a soft IP solution and associated documentation, available for
download at:
www.altera.com/patches/xaui-softip/xaui-softip-fix-reva.zip
This soft IP should be integrated into the XAUI receiver data path.
This issue is fixed in production devices.
The peripheral clock (PCLK) from the transmitter PMA in channel 3 of GXBR0 and
GXBL0 feed a PCLK through a multiplexer from a periphery clock region that is not
adjacent to channel 3, causing additional routing delays. This delay causes one
particular channel out of a total of 24 channels (configured in Basic [PMA Direct]
mode) on either side of the device to not close timing for data rates ≥ 6.375.
The workaround is to route the tx_clkout signal for channel 3 of GXBR0 and GXBL0
to a GPLL that is closest to the affected channel to re-generate the clock for the
transmit side logic.
For more information about implementing this workaround with a GPLL, refer to
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional
This issue is fixed in production devices.
shows the channel skew.
S = Start of Packet
T = End of Packet
D = Data Packet
A = Alignment Character
K = Lane Synchronization Character
R = Clock Rate Compensation Character
channel 0
channel 1
channel 2
channel 3
channel 0
channel 1
channel 2
channel 3
...
K
K
K
K
K
K
K
R
R
R
R
R
R
R
K
S
D
D
D
R
D
D
D
D
D
D
D
D
D
D
S
...
...
...
...
...
...
...
D
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
D
D
D
D
...
D
D
D
D
K
K
D
K
K
T
T
March 2011 Altera Corporation
Stratix IV GX ES Family Issues
Mode.
D
A
A
A
A
A
A
A
R
R
R
R
A
R
R
R
R
R
R
R
R
R
R
R
K
K
K
K
R
K
K
K