EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 3

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Production Devices for Stratix IV GX Devices
March 2011 Altera Corporation
Quartus II Software Incorrect Setting for Transceiver CDR in All Modes
Except PCIe Mode
Dynamic Reconfiguration Issue Between PCIe Mode and Any Other
Transceiver Mode
Quartus II Mapping Issue with PCIe Interfaces Using the Hard IP Block
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The Quartus II software versions up to and including 10.0 SP1 incorrectly set the clock
and data recovery (CDR) unit when the transceiver channel is configured in any mode
except PCIe mode and the CDR is configured to automatic lock mode. When there are
no data transitions on the transceiver data inputs for an extended period of time (in
the ms range), the CDR may keep the rx_freqlocked signal asserted. The CDR does
not return to the lock-to-reference state and incorrect data may be recovered.
The transceiver channels configured in PCIe mode are NOT affected by this issue.
Solution
This issue is fixed in the Quartus II software versions 10.1 and later. Altera
recommends upgrading to the latest Quartus II software and recompiling your
design. For complete details of the solution, refer to the
Additionally, software patches are available for the Quartus II software versions
9.1 SP2 and 10.0 SP1.
To download and install the patch, refer to the
If you need additional support, file a service request at Altera’s mysupport.
If your application uses dynamic reconfiguration to change the transceiver channel
between PCIe mode and any other transceiver mode, the transceiver may not be
initialized correctly, resulting in receiver bit errors.
This problem only affects dynamic reconfiguration between PCIe mode and any other
transceiver mode. Dynamic reconfiguration between any transceiver modes other
than PCIe mode is not affected.
Workaround
If you see bit errors, apply the reset sequence described in the
Solution.
If you need additional support, file a service request at Altera’s mysupport.
The Quartus II software versions 9.1, 9.1 SP1, and 9.1 SP2 incorrectly allow logical
channel 0 to be placed in any physical channel for ×1 and ×4 PCIe Gen1 interfaces
with the hard IP block. For correct operation with the hard IP block, logical channel 0
must be placed in physical channel 0.
Transceiver CDR
Transceiver CDR Solution.
Errata Sheet for Stratix IV GX Devices
Reset Sequence
Solution.
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