EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 24

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Page 24
Table 6. Updated Data Rate Ranges and Behavior for Affected Configurations with Stratix IV GX ES Devices (Part 1 of 2)
Errata Sheet for Stratix IV GX Devices
PCIe Gen2 ×8 functional mode with hard IP
using CMU PLL or ATX PLL
Basic ×8 (PCS+PMA Bonded) functional
mode with CMU PLL
×8 and ×N Clock Line Timing Issue for Transceivers
Configuration
Use the Stratix IV GX PowerPlay EPE version 9.0.1 to estimate current and
power/thermal requirements for Stratix IV GX -2 speed grade ES devices with the
required higher power supply levels. The Stratix IV GX PowerPlay EPE version 9.0
reflects current and power estimates for production devices at data sheet
specifications only.
Production devices will not operate at these higher power supply levels. If needed,
design your power supplies to support dropping power supply levels back to the data
sheet specification for production devices.
There are no reliability issues with Stratix IV ES devices at these higher power supply
levels.
Transceiver channels in Stratix IV GX ES devices may transmit incorrect serial bits due
to skew accumulated from ×8 and ×N clock lines. This issue will lead to loss-of-link
synchronization.
The following configurations are affected:
■
■
■
■
■
■
■
Table 6
(system constraints permitting) if you are using ES devices.
PCIe Gen2 ×8 functional mode with hard IP using CMU PLL or ATX PLL (the ATX
PLL will be supported in the PCIe Compiler version 9.1). For more information,
refer to the Incorrect Link Training for Stratix IV GX Gen2 x8 Hard IP Implementation
section in the
Basic ×8 (PCS+PMA Bonded) functional mode with CMU PLL
PMA direct mode ×N with CMU PLL or ATX PLL
PCIe Gen2 ×8 functional mode using CMU PLL or ATX PLL
PCIe Gen2 ×4 functional mode using ATX PLL
(OIF) CEI PHY interface functional mode with ATX PLL
Basic functional mode ×1/×4/×8 with ATX PLL
(1)
lists the updated data rate ranges and behavior for the affected configurations
MegaCore IP Library Release Notes and Errata document.
For more information about this issue, refer to the Incorrect Link Training for
Stratix IV GX Gen2 x8 Hard IP Implementation section in the
Library Release Notes and Errata
■
■
5 Gbps to 6.5 Gbps (-2 speed grade with higher transceiver power
supplies. V
set to 1.2 ± 0.05 V)
600 Mbps to 5 Gbps (-2, -2x, -3, and -4 speed grades)
CCR_L/R
Updated Data Rate Ranges and Behavior
, V
CCT_L/R
, and V
document.
CCL_GXB_L/Rn
March 2011 Altera Corporation
Stratix IV GX ES Family Issues
power supplies must be
MegaCore IP