EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 740
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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2–68
Stratix IV Device Handbook Volume 2: Transceivers
Figure 2–36. Sixteen Non-Bonded Receiver Channels without Rate Match for Example 7
Because the recovered clock rx_clkout signals from all 16 channels have a 0 PPM
frequency difference, you can use a single rx_clkout to clock the receiver phase
compensation FIFO in all 16 channels. This results in only one global, regional, or
global and regional clock resource being used instead of 16. To achieve this, you must
select the receiver phase compensation FIFO read clocks instead of the Quartus II
software default selection, as described in
Compensation FIFO Read Clock” on page
Channel [15:12]
Channel [3:0]
Channel [11:8]
Channel [7:4]
and Status
and Status
RX Data
and Status
and Status
RX Data
RX Data
Logic
RX Data
Logic
Logic
Logic
FPGA
Fabric
rx_coreclk[7]
rx_coreclk[6]
rx_coreclk[3]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
rx_coreclk[15]
rx_coreclk[14]
rx_coreclk[13]
rx_coreclk[12]
rx_coreclk[11]
rx_coreclk[10]
rx_coreclk[9]
rx_coreclk[8]
rx_coreclk[5]
rx_coreclk[4]
“User-Selected Receiver Phase
2–69.
Chapter 2: Transceiver Clocking in Stratix IV Devices
rx_clkout[7]
rx_clkout[6]
rx_clkout[5]
rx_clkout[4]
rx_clkout[3]
rx_clkout[2]
rx_clkout[1]
rx_clkout[0]
rx_clkout[15]
rx_clkout[14]
rx_clkout[13]
rx_clkout[12]
rx_clkout[11]
rx_clkout[10]
rx_clkout[9]
rx_clkout[8]
FPGA Fabric-Transceiver Interface Clocking
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR3
Transceiver Block GXBR2
February 2011 Altera Corporation
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
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