EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 907
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–31. Input Reference Clocks Connections to the Transceiver Channels
Note to
(1) Depending on the mode you select, the PCS unit may or may not be present.
February 2011 Altera Corporation
Figure
5–31:
(Identification
number = 2)
(Identification
number = 1)
Refclk0
Refclk1
156 .25 MHz
125MHz
Figure 5–31
to the transceiver channels are based on what you set as the input clock source for
each of the CMU transmitter PLLs within a transceiver block.
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU0 PLL.
CMU0 PLL, this clock mux
shows an example scenario where the input reference clock connections
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU1 PLL.
CMU1 PLL, this clock mux
clock
mux
clock
mux
CMU Channels
CMU0 PLL
CMU1 PLL
3.125 Gbps
1 Gbps
TX PLL
Logical
select
TX PLL
clock
Logical
mux
select
clock
mux
Full Duplex Transceiver Channel 1
Full Duplex Transceiver Channel 2
Stratix IV Device Handbook Volume 2: Transceivers
DIVIDER
TX CHANNEL 1
RX CHANNEL 1
LOCAL
3.125 Gbps
DIVIDER
RX CHANNEL 2
RX CDR
TX CHANNEL 2
LOCAL
RX CDR
1 Gbps
TX PMA + TX PCS
RX PMA + RX PCS
TX PMA + TX PCS
RX PMA + RX PCS
3.125 Gbps
3.125 Gbps
1 Gbps
1 Gbps
(1)
(1)
5–61
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