EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 823
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
Figure 4–9. Sample Reset Sequence of Receiver Only Channel—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
February 2011 Altera Corporation
Output Status Signals
CDR Control Signals
Figure
LTR_LTD
LTD_Manual
Reset Signals
rx _ analogreset
rx _ locktorefclk
rx _ digitalreset
rx _ locktodata
4–9:
rx _ pll _ locked
duration, refer to the
duration, refer to the
busy
As shown in
reset steps:
1. After power up, wait for the busy signal to be de-asserted.
2. De-assert the rx_analogreset signal.
3. Keep the rx_digitalreset signal asserted during this time period. After you
4. Wait for the rx_freqlocked signal to go high.
5. When rx_freqlocked goes high (marker 3), from that point onwards, wait for
Receiver Only Channel—Receiver CDR in Manual Lock Mode
This configuration contains only a receiver channel. If you create a Receiver Only
instance in the ALTGX MegaWizard Plug-In Manager with receiver CDR in manual
lock mode, use the reset sequence shown in
de-assert the rx_analogreset signal, the receiver CDR starts locking to the
receiver input reference clock.
at least t
point, the receiver is ready to receive data.
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
LTD_Auto
Figure
Two parallel clock cycles
1
4–8, for the receiver in CDR automatic lock mode, follow these
, then de-assert the rx_digitalreset signal (marker 4). At this
2
3
t
LTR_LTD_Manual (1)
Figure
t
LTD_Manual (2)
4
4
chapter.
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
4–9.
5
4–17
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