XC3S100E-5TQG144C Xilinx Inc, XC3S100E-5TQG144C Datasheet - Page 141
![IC FPGA SPARTAN-3E 100K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S100E-5TQG144C
Manufacturer Part Number
XC3S100E-5TQG144C
Description
IC FPGA SPARTAN-3E 100K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-5TQG144C
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
108
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S100E-5TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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18 x 18 Embedded Multiplier Timing
Table 102: 18 x 18 Embedded Multiplier Timing
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Combinatorial Delay
T
Clock-to-Output Times
T
T
T
Setup Times
T
T
T
Hold Times
T
T
T
Clock Frequency
F
MULT
MSCKP_P
MSCKP_A
MSCKP_B
MSDCK_P
MSDCK_A
MSDCK_B
MSCKD_P
MSCKD_A
MSCKD_B
MULT
Symbol
Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
R
Combinatorial multiplier propagation delay from the A and B
inputs to the P outputs, assuming 18-bit inputs and a 36-bit
product (AREG, BREG, and PREG registers unused)
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
the PREG register
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
either the AREG or BREG register
Data setup time at the A or B input before the active
transition at the CLK when using only the PREG output
register (AREG, BREG registers unused)
Data setup time at the A input before the active transition at
the CLK when using the AREG input register
Data setup time at the B input before the active transition at
the CLK when using the BREG input register
Data hold time at the A or B input after the active transition
at the CLK when using only the PREG output register
(AREG, BREG registers unused)
Data hold time at the A input after the active transition at the
CLK when using the AREG input register
Data hold time at the B input after the active transition at the
CLK when using the BREG input register
Internal operating frequency for a two-stage 18x18
multiplier using the AREG and BREG input registers and
the PREG output register
(2)
Description
(1)
(2)
(3)
www.xilinx.com
(3)
(3)
(2)
(3)
(3)
–
3.54
0.20
0.35
0.03
0.04
Min
0.97
0
-
-
-
-5
DC and Switching Characteristics
4.34
Speed Grade
Max
0.98
4.42
270
-
-
-
-
-
-
(1)
–
3.98
0.23
0.39
0.04
0.05
Min
0.97
0
-
-
-
-4
4.88
Max
1.10
4.97
240
-
-
-
-
-
-
(1)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
141
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