XC3S100E-5TQG144C Xilinx Inc, XC3S100E-5TQG144C Datasheet - Page 153
![IC FPGA SPARTAN-3E 100K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S100E-5TQG144C
Manufacturer Part Number
XC3S100E-5TQG144C
Description
IC FPGA SPARTAN-3E 100K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-5TQG144C
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
108
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S100E-5TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Master Serial and Slave Serial Mode Timing
Table 116: Timing for the Master Serial and Slave Serial Configuration Modes
DS312-3 (v3.8) August 26, 2009
Product Specification
(Input/Output)
Notes:
1.
2.
(Open-Drain)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
DOUT
CCLK
DIN
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Figure 75: Waveforms for Master Serial and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
www.xilinx.com
T
CCD
Bit 1
Table
77.
T
T
Master
Master
Master
Slave/
MCCL
Slave
Slave
Slave
SCCL
Both
Both
Both
DC and Switching Characteristics
Bit n
1/F
CCSER
T
CCO
Bit n-64
All Speed Grades
Bit n+1
11.0
Min
1.5
T
T
0
0
0
MCCH
SCCH
See
See
See
See
Bit n-63
Table 114
Table 115
Table 114
Table 115
66
Max
10.0
20
-
-
(2)
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
153
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