XC3S100E-5TQG144C Xilinx Inc, XC3S100E-5TQG144C Datasheet - Page 189
![IC FPGA SPARTAN-3E 100K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S100E-5TQG144C
Manufacturer Part Number
XC3S100E-5TQG144C
Description
IC FPGA SPARTAN-3E 100K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-5TQG144C
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
108
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S100E-5TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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User I/Os by Bank
Table 142
distributed between the four I/O banks on the PQ208 pack-
age.
Table 142: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
indicates how the 158 available user-I/O pins are
R
I/O Bank
0
1
2
3
Maximum
158
I/O
38
40
40
40
I/O
18
23
58
9
8
www.xilinx.com
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
ation.
INPUT
25
6
7
6
6
All Possible I/O Pins by Type
DUAL
21
24
46
1
0
VREF
13
5
3
2
3
Pinout Descriptions
(1)
CLK
0
0
16
8
8
(2)
(2)
(1)
189
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