XC3SD1800A-4CSG484C Xilinx Inc, XC3SD1800A-4CSG484C Datasheet - Page 54
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-4CSG484C
Manufacturer Part Number
XC3SD1800A-4CSG484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4CSG484C
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
No. Of Logic Blocks
37440
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
309
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1537
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Master Serial and Slave Serial Mode Timing
X-Ref Target - Figure 11
Table 50: Timing for the Master Serial and Slave Serial Configuration Modes
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
(Input/Output)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
(Open-Drain)
CCO
DCC
CCD
CCH
CCL
CCSER
Symbol
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
CCLK
DOUT
DIN
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the
CCLK input pin
Figure 11: Waveforms for Master Serial and Slave Serial Configuration
(2)
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
CCD
Bit 1
Table
7.
T
T
Master
Master
Master
Master
Slave/
MCCL
SCCL
Slave
Slave
Slave
Slave
Both
Both
Bit n
1/F
CCSER
T
CCO
Bit n-64
Bit n+1
All Speed Grades
Min
1.5
0.0
1.0
T
7
0
0
T
SCCH
MCCH
See
See
See
See
Bit n-63
Table 48
Table 49
Table 48
Table 49
Max
100
100
10
–
–
–
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
ns
54