XC3SD1800A-4CSG484C Xilinx Inc, XC3SD1800A-4CSG484C Datasheet - Page 72
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-4CSG484C
Manufacturer Part Number
XC3SD1800A-4CSG484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4CSG484C
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
No. Of Logic Blocks
37440
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
309
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1537
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
User I/Os by Bank
Table 64
The AWAKE pin is counted as a dual-purpose I/O.
Table 64: User I/Os Per Bank for the XC3SD1800A in the CS484 Package
Table 65: User I/Os Per Bank for the XC3SD3400A in the CS484 Package
Footprint Migration Differences
There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package.
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Notes:
1.
Top
Right
Bottom
Left
Top
Right
Bottom
Left
Package
Package
TOTAL
19 VREF are on INPUT pins.
TOTAL
19 VREF are on INPUT pins.
Edge
Edge
and
Table 65
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
indicates how the user-I/O pins are distributed between the four I/O banks on the CS484 package.
Maximum I/Os
Maximum I/O
Input-Only
Input-Only
and
and
309
309
77
78
76
78
77
78
76
78
156
156
I/O
I/O
49
23
33
51
49
23
33
51
www.xilinx.com
INPUT
INPUT
Spartan-3A DSP FPGA Family: Pinout Descriptions
13
13
41
13
13
41
9
6
9
6
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
30
21
52
30
21
52
1
0
1
0
VREF
VREF
28
28
6
8
8
6
6
8
8
6
(1)
(1)
CLK
CLK
32
32
8
8
8
8
8
8
8
8
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