XC3SD1800A-4FGG676I Xilinx Inc, XC3SD1800A-4FGG676I Datasheet - Page 32
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-4FGG676I
Manufacturer Part Number
XC3SD1800A-4FGG676I
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4FGG676I
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
No. Of Logic Blocks
4224
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
519
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
591
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
160
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions.
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of V
High logic level of V
Some standards also require the application of a bias
voltage to the V
input-switching threshold. The measurement point of the
Input signal (V
and V
The Output test setup is shown in
voltage V
end of which is connected to the Output. For each standard,
R
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
Table 26: Test Methods for Timing Measurement at I/Os
DS610 (v3.0) October 4, 2010
Product Specification
Single-Ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
T
and V
Signal Standard
H
(IOSTANDARD)
.
T
T
is applied to the termination resistor R
generally take on the standard values
Table 26
Rising
Falling
Rising
Falling
M
REF
) is commonly located halfway between V
H
pins of a given bank to properly set the
lists the conditions to use for each
is applied to the Input under test.
V
REF
0.75
1.25
1.25
0.9
0.9
0.9
1.1
0.9
0.9
1.5
1.5
–
–
–
–
–
–
–
–
Figure
(V)
8. A termination
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note
Note
V
Inputs
L
T
0
0
0
0
0
0
– 0.75
– 0.75
– 0.75
– 0.75
L
, the other
(V)
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
and a
3
3
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
L
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note
Note
V
LVCMOS, LVTTL), then R
open connection, and V
measurement point (V
used at the Output.
X-Ref Target - Figure 8
H
3.3
3.3
2.5
1.8
1.5
1.2
+ 0.75
+ 0.75
+ 0.75
+ 0.75
(V)
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
3
3
Notes:
1.
FPGA Output
The names shown in parentheses are
used in the IBIS file.
Figure 8: Output Test Setup
R
T
1M
1M
1M
1M
1M
1M
25
25
25
25
50
50
50
25
50
50
25
50
25
50
25
(Ω)
Outputs
M
T
) that was used at the Input is also
is set to zero. The same
T
V
is set to 1MΩ to indicate an
T
(2)
(V
V
REF
R
C
0.75
1.25
1.25
T
3.3
3.3
1.5
0.9
0.9
1.8
0.9
0.9
1.5
1.5
T
L
0
0
0
0
0
0
0
0
(V)
(R
)
(C
V
DS312-3_04_102406
M
REF
REF
(V
)
MEAS
)
Inputs and
Outputs
)
V
V
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
0.94
2.03
0.94
2.03
M
1.4
0.9
0.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(V)
32