XC3SD1800A-4FGG676I Xilinx Inc, XC3SD1800A-4FGG676I Datasheet - Page 58
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-4FGG676I
Manufacturer Part Number
XC3SD1800A-4FGG676I
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4FGG676I
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
No. Of Logic Blocks
4224
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
519
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
591
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
160
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 14
(Open-Drain)
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
DS610 (v3.0) October 4, 2010
Product Specification
T
T
T
T
T
T
T
T
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
Byte 0
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
New ConfigRate active
Minimum
T
CCLK1
Address
T
50
CCO
0
0
5
Data
See T
T
DCC
See
See
See
SMDCC
T
Address
CCLKn
Maximum
Table 46
Table 46
Table 50
Data
in
–
–
5
–
Table 51
Address
DS529-3_05_090610
T
Data
CCD
T
cycles
Units
CCLK1
ns
ns
ns
58