XC3SD1800A-4FGG676I Xilinx Inc, XC3SD1800A-4FGG676I Datasheet - Page 41

• Manufacturer Part Number: XC3SD1800A-4FGG676I
• Description: SPARTAN-3ADSP FPGA 1800K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD1800A-4FGG676I

• Total Ram Bits: 1548288
• Number Of Logic Elements/cells: 37440
• Number Of Labs/clbs: 4160
• Number Of I /o: 519
• Number Of Gates: 1800000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA
• No. Of Logic Blocks: 4224
• No. Of Gates: 1800000
• No. Of Macrocells: 37440
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 519
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Block RAM Timing
Table 33: Block RAM Timing
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Clock-to-Output Times
T
T
Setup Times
T
T
T
T
T
T
Hold Times
T
T
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
RCKO_DOA_NC
RCKO_DOA
RCCK_ADDR
RDCK_DIB
RCCK_ENB
RCCK_WEB
RCCK_REGCE
RCCK_RST
RCKC_ADDR
RCKC_DIB
RCKC_ENB
RCKC_WEB
RCKC_REGCE
RCKC_RST
BPWH
BPWL
BRAM
Symbol
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the active transition at
the CLK input to data appearing at the DOUT output
Clock CLK to DOUT output (with output register)
Setup time for the ADDR inputs before the active transition at the CLK
input of the block RAM
Setup time for data at the DIN inputs before the active transition at the
CLK input of the block RAM
Setup time for the EN input before the active transition at the CLK input
of the block RAM
Setup time for the WE input before the active transition at the CLK input
of the block RAM
Setup time for the CE input before the active transition at the CLK input
of the block RAM
Setup time for the RST input before the active transition at the CLK
input of the block RAM
Hold time on the ADDR inputs after the active transition at the CLK
input
Hold time on the DIN inputs after the active transition at the CLK input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Hold time on the CE input after the active transition at the CLK input
Hold time on the RST input after the active transition at the CLK input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Table
7.
0.40
0.29
0.51
0.64
0.34
0.22
0.09
0.09
0.09
0.09
0.09
0.09
1.56
1.56
Min
–
–
0
-5
Speed Grade
Max
2.38
1.24
320
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.46
0.33
0.60
0.75
0.40
0.25
0.10
0.10
0.10
0.10
0.10
0.10
1.79
1.79
Min
–
–
0
-4
Max
2.80
1.45
280
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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