XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 36

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Fundamentals
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in
support a variety of voltage requirements.
Table 18:
Module 2 of 4
32
LVTTL
LVCMOS2
LVCMOS18
SSTL3 I & II
SSTL2 I & II
GTL
GTL+
HSTL I
HSTL III & IV
CTT
AGP-2X
PCI33_3
PCI66_3
BLVDS & LVDS
LVPECL
Standard
I/O
Virtex-E Supported I/O Standards
Output
V
N/A
N/A
3.3
2.5
1.8
3.3
2.5
1.5
1.5
3.3
3.3
3.3
3.3
2.5
3.3
CCO
Input
V
Table
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
3.3
3.3
CCO
18, each buffer type can
Input
V
1.50
1.25
0.80
0.75
0.90
1.50
1.32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.0
REF
Voltage (V
Termination
Board
1.50
1.25
1.20
1.50
0.75
1.50
1.50
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
www.xilinx.com
1-800-255-7778
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)
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
LVTTL — Low-Voltage TTL
The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3 V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3 V output source voltage (V
does not require the use of a reference voltage (V
termination voltage (V
LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard (JESD
8.-5) used for general purpose 2.5 V applications. This stan-
dard requires a 2.5 V output source voltage (V
does not require the use of a reference voltage (V
board termination voltage (V
LVCMOS18 — 1.8 V Low Voltage CMOS
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (V
(V
PCI — Peripheral Component Interface
The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (V
ever, it does require a 3.3 V output source voltage (V
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation for this stan-
dard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5 V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
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http://www.jedec.org
) is not required.
REF
) or a board termination voltage (V
REF
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DS025-2 (v2.3) November 19, 2002
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CCO
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CCO
REF
REF
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CCO
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