AT94K05AL-25AQU Atmel, AT94K05AL-25AQU Datasheet - Page 156
AT94K05AL-25AQU
Manufacturer Part Number
AT94K05AL-25AQU
Description
IC FPSLIC 5K GATE 25MHZ 100-TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Datasheet
1.AT94K05AL-25AJI.pdf
(204 pages)
Specifications of AT94K05AL-25AQU
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 4-32.
156
(TWSR)
Status
Code
$C0
$C8
$A8
$B0
$B8
AT94KAL Series FPSLIC
Own SLA+R has been
received;
ACK has been returned
Arbitration lost in
SLA+R/W as Master;
own SLA+R has been
received;
ACK has been returned
Data byte in TWDR has
been transmitted;
ACK has been received
Data byte in TWDR has
been transmitted;
NOT ACK has been
received
Last data byte in TWDR
has been transmitted
(TWAE = “0”);
ACK has been received
Serial Bus and 2-wire
Status of the 2-wire
Serial Hardware
Status Codes for Slave Transmitter Mode
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
Load data byte
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
To/From TWDR
Application Software Response
STA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
STO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWEA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition
will be transmitted when the bus becomes
free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition
will be transmitted when the bus becomes
free
Next Action Taken by 2-wire
Serial Hardware
1138I–FPSLI–1/08
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