AT94K05AL-25AQU Atmel, AT94K05AL-25AQU Datasheet - Page 26

• Manufacturer Part Number: AT94K05AL-25AQU
• Description: IC FPSLIC 5K GATE 25MHZ 100-TQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.3
26
AT94KAL Series FPSLIC
B Side
Table 3-2.
The B side is not partitioned; the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes.
• The B side is accessed by the FPGA/Configuration Logic.
• The B side is accessed by the AVR with ST and LD instructions in DBG mode for code self-
• AVR data to FPGA addressing is 1:1 mapping.
• AVR program to FPGA addressing requires 16-bit to 8-bit mapping and an understanding of
modify.
the partitions in
To activate the debug mode and allow the AVR to access the program code space (with ST
– see
$3A ($5A) register has to be set. When this bit is set, SCR36 and SCR37 are ignored – you
can overwrite anything in the AVR program memory.
The FPGA memory access interface should be disabled while in debug mode. This is to
ensure that there is no contention between the FPGA address and data signals and the
AVR-generated address and data signals. To ensure the AVR has control over the “B side”
memory interface, the FMXOR bit (bit 3) of the SFTCR $3A ($5A) register should be used in
conjunction with the SCR63 system control register bit.
The FMXOR bit is XORed with the System Control Register’s Enable FPGA SRAM Interface
bit (SCR63). The behavior when this bit is set to 1 is dependent on how the SCR was initial-
ized. If the Enable FPGA SRAM Interface bit (SCR63) in the SCR is 0, the FMXOR bit
enables the FPGA SRAM Interface when set to 1. If the Enable FPGA SRAM Interface bit in
the SCR is 1, the FMXOR bit disables the FPGA SRAM Interface when set to 1. During AVR
reset, the FMXOR bit is cleared by the hardware.
Even though the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes, an awareness of the 2K x 8 partitions (or SRAM labels) is required if Frame
(and AVR debug mode) read/writes are to be meaningful to the AVR.
Address Range
$07FF – $0000
$0FFF – $0800
$17FF – $1000
$1FFF – $1800
$27FF – $2000
$2FFF – $2800
$37FF – $3000
$3FFF – $3800
Figure 3-4
AVR Data Decode for SRAM 0:17 (16K8)
Table
– and LD – see
3-3.
Figure 3-5
SRAM
00
01
02
03
04
05
06
07
– instructions), the DBG bit (bit 1) of the SFTCR
Comments
AVR Data Read/Write
AVR Data Read/Write
CR41:40 = 11,10,01
CR41:40 = 11,10
CR41:40 = 11
1138I–FPSLI–1/08