CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 24
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CY7C63231A-PXC
Manufacturer Part Number
CY7C63231A-PXC
Description
IC MCU 3K USB LS PERIPH 18-DIP
Manufacturer
Cypress Semiconductor Corp
Series
enCoRe™r
Specifications of CY7C63231A-PXC
Applications
USB Microcontroller
Core Processor
M8B
Program Memory Type
OTP (3 kB)
Controller Series
CY7C632xx
Ram Size
96 x 8
Interface
USB
Number Of I /o
10
Voltage - Supply
3.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
18-DIP (0.300", 7.62mm)
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Processor Series
CY7C63xx
Core
M8B
Data Bus Width
16 bit
Program Memory Size
3 KB
Data Ram Size
96 B
Interface Type
PS2, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
10
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C63231A-PXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Bit 3: USB Bus Activity
Bit [2:0]: D+/D– Forcing Bit [2:0]
Table 13-1. Control Modes to Force D+/D– Outputs
Document #: 38-08028 Rev. *B
Note:
2.
The Bus Activity bit is a “sticky” bit that detects any non-idle USB event has occurred on the USB bus. Once set to HIGH by
the SIE to indicate the bus activity, this bit retains its logical HIGH value until firmware clears it. Writing a ‘0’ to this bit clears
it; writing a ‘1’ preserves its value. The user firmware should check and clear this bit periodically to detect any loss of bus
activity. Firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024-ms timer interrupt service routine is
normally used to check and clear the Bus Activity bit.
1 = There has been bus activity since the last time this bit was cleared. This bit is set by the SIE.
0 = No bus activity since last time this bit was cleared (by firmware).
Forcing bits allow firmware to directly drive the D+ and D– pins, as shown in Table 13-1. Outputs are driven with controlled
edge rates in these modes for low EMI. For forcing the D+ and D– pins in USB mode, D+/D– Forcing Bit 2 should be 0. Setting
D+/D– Forcing Bit 2 to ‘1’ puts both pins in an open-drain mode, preferred for applications such as PS/2 or LED driving.
For PS/2 operation, the D+/D- Forcing Bit [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.
D+/D– Forcing Bit [2:0]
000
001
010
011
100
101
110
111
FOR
FOR
Not forcing (SIE controls driver)
Force SE0 (D– LOW, D+ LOW)
Force K (D+ HIGH, D– LOW)
Force J (D+ LOW, D– HIGH)
Force D– LOW, D+ LOW
Force D– HiZ, D+ LOW
Force D– LOW, D+ HiZ
Force D– HiZ, D+ HiZ
Control Action
CY7C63221/31A
enCoRe™ USB
PS/2 Mode
Application
USB Mode
Any Mode
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