CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 38

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

The response of the SIE can be summarized as follows:
Document #: 38-08028 Rev. *B
1. The SIE will only respond to valid transactions, and will ignore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs
3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa versa.
5. The IN and OUT PID status is updated at the end of a transaction.
6. The SETUP PID status is updated at the beginning of the Data packet phase.
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
Table 20-2. Decode table for Table 20-3: “Details of Modes for Differing Traffic Conditions”
3
Legend:
Endpoint Mode
during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of these registers, and only if that
read happens after the transaction completes. This represents about a 1-µs window in which the CPU is locked from register
writes to these USB registers. Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to
unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made during the previous transaction.
Encoding
2
(SETUP, IN,OUT)
Received Token
1
0
Token
count
The number of received bytes
UC: unchanged
x: don’t care
available for Control endpoint only
Properties of incoming
packet
buffer
The quality status of the DMA buffer
FOR
FOR
dval
The validity of the received data
DTOG
Data 0/1 (Bit 7, Figure 14-4)
TX: transmit
RX: receive
Changes to the internal register made by the SIE as a result of
DVAL
Data Valid (Bit 6, Figure 14-4)
COUNT
Bit[3:0], Figure 14-4
the incoming token
Setup
TX0: transmit 0-length packet
(Bit[7:5], Figure 14-2)
PID Status Bits
In
Out
ACK
Acknowledge transaction completed
(Bit4,Figure 14-2/3)
CY7C63221/31A
enCoRe™ USB
End Point
Mode
3
Endpoint Mode changed
by the SIE.
2 1 0 Response
SIE’s Response
Page 38 of 50
Interrupt?
Int
[+] Feedback