ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 137

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPHA and SPICPOL bits be configured
the same for the master and slave devices.
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of SS according to the
SPICON bit setting. In slave mode, SS is always an input.
In SPI master mode, the SS (P0.7/T1) can be used to control
data transfer to a slave device. In the automatic slave select
control mode, the SS is asserted low to select the slave device
and then raised to deselect the slave device after the transfer is
complete. Automatic slave select control is enabled by setting the
AUTO_SS bit in the SPI Configuration SFR 1 (SPIMOD1,
Address 0xE8).
In a multimaster system, the SS can be configured as an input so
that the SPI peripheral can operate as a slave in some situations
and as a master in others. In this case, the slave selects for the
slaves controlled by this SPI peripheral should be generated
with general I/O pins.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I
buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of
a byte transfer. Continuous mode is enabled by setting the
SPICONT bit (Bit 7) in the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9). The SPI peripheral also offers a single byte
read/write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the SPICONT bit in the SPI
Configuration SFR 2 (SPIMOD2, 0xE9). The following
procedures show the sequence of events that should be
performed for each master operating mode. Based on the SS
configuration, some of these events take place automatically.
Procedures for Using SPI as a Master
Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1.
2.
3.
4.
5.
6.
Write to the SPI2CTx SFR.
SS is asserted low, and a write routine is initiated.
The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
2
C transmit
Rev. B | Page 137 of 152
Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1.
2.
3.
4.
5.
6.
7.
Figure 110 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous mode
is not used, a short delay is inserted between transfers.
Note that reading the content of the SPI/I
(SPI2CRx, Address 0x9B) should be done using a 2-cycle
instruction set such as MOV A or SPI2CRX. Using a 3-cycle
instruction such as MOV 0x3D or SPI2CRX does not transfer
the right information into the target register.
(MANUAL SS CONTROL)
Write to the SPI2CTx SFR.
SS is asserted low, and a write routine is initiated.
Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.
Transfer continues until the SPI2CTx register and transmit
shift registers are empty.
The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
Figure 110. Automatic Chip Select and Continuous Mode Output
AUTO_SS = 1
AUTO_SS = 1
AUTO_SS = 0
SPICONT = 1
SPICONT = 0
SPICONT = 0
DOUT
SCLK
DOUT
DOUT
SCLK
SCLK
DIN
SS
DIN
DIN
SS
SS
DOUT1
DOUT1
DIN1
DIN1
DOUT1
DIN1
2
C receive buffer SFR
DOUT2
DIN2
DOUT2
DIN2
DOUT2
DIN2