CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet
CY7C65113-SC
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... USB Hub with Microcontroller Cypress Semiconductor Corporation Document #: 38-08002 Rev. *B • 3901 North First Street • CY7C65013 CY7C65113 , San Jose CA 95134 • 408-943-2600 Revised March 12, 2003 ...
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... USB Bus Reset Interrupt ........................................................................................................ 28 14.4 Timer Interrupt ....................................................................................................................... 28 14.5 USB Endpoint Interrupts ........................................................................................................ 28 14.6 USB Hub Interrupt .................................................................................................................. 28 14.7 GPIO Interrupt ........................................................................................................................ Interrupt ............................................................................................................................ 29 15.0 USB OVERVIEW ......................................................................................................................... 30 15.1 USB Serial Interface Engine (SIE) ......................................................................................... 30 15.2 USB Enumeration .................................................................................................................. 30 Document #: 38-08002 Rev. *B TABLE OF CONTENTS CY7C65013 CY7C65113 Page ...
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... Endpoint Mode/Count Registers Update and Locking Mechanism ........................................ 39 18.0 USB MODE TABLES .................................................................................................................. 41 19.0 REGISTER SUMMARY ............................................................................................................... 45 20.0 SAMPLE SCHEMATIC ............................................................................................................... 47 21.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 47 22.0 ELECTRICAL CHARACTERISTICS ........................................................................................... 48 23.0 SWITCHING CHARACTERISTICS 24.0 ORDERING INFORMATION ....................................................................................................... 49 25.0 PACKAGE DIAGRAMS .............................................................................................................. 49 Document #: 38-08002 Rev. *B TABLE OF CONTENTS (continued) (f OSC = 6.0 MHz) ..................................................................................... 48 CY7C65013 CY7C65113 Page ...
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... Figure 17-1. USB Device Address Registers ....................................................................................... 36 Figure 17-2. USB Device Endpoint Zero Mode Registers ................................................................... 37 Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................ 38 Figure 17-4. USB Endpoint Counter Registers .................................................................................... 39 Figure 17-5. Token/Data Packet Flow Diagram ................................................................................... 40 Document #: 38-08002 Rev. *B LIST OF FIGURES CY7C65013 CY7C65113 Page ...
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... Table 18-1. USB Register Mode Encoding .......................................................................................... 41 Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Conditions” ............. 42 Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend) 43 Document #: 38-08002 Rev. *B LIST OF TABLES CY7C65013 CY7C65113 Page ...
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... Improved output drivers to reduce electromagnetic interference (EMI) • Operating voltage from 4.0V to 5.5V DC • Operating temperature from • CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages • CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages • Industry-standard programmer support. Document #: 38-08002 Rev. *B CY7C65013 ...
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... Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same “GPIO” interrupt vector. CY7C65113 The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated per pin (typical) sink current. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Clock The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal phase-locked loop (PLL)-based clock generator ...
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... High Current P3[1] Outputs PORT 3 P3[0] CY7C65013 only comp. SCLK SDATA Interface 2 *I C-compatible interface enabled by firmware through P2[1:0] or P1[1:0] CY7C65013 CY7C65113 D+[0] Upstream USB Port D–[0] Downstream USB Ports USB D+[1] D–[1] Transceiver USB D+[4] Transceiver D–[4] USB D+[5] Transceiver D– ...
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... GPIO Port 0 capable of sinking 7 mA (typical). 11, 15, 12, 16, 13, 17, 14, 18 P1[2:0] GPIO Port 1 capable of sinking 7 mA (typical). 25, 27, 26 GPIO Port 2 capable of sinking 12 mA (typical). GPIO Port 3, capable of sinking 12 mA (typical). 2 6-MHz crystal or external clock input. CY7C65013 CY7C65113 CY7C65113 28-pin SOIC P1[ P1[0] ...
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... Global Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 0x23 R Pending Interrupt Vector Read/Clear 0x24 R Lower Eight Bits of Free-running Timer (1 MHz) 0x25 R Upper Four Bits of Free-running Timer 0x26 W Watchdog Reset Clear 2 0x28 R Status and Control 2 0x29 R Data CY7C65013 CY7C65113 Description Function Page ...
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... Microprocessor Status and Control Register opcode cycles MNEMONIC 7 NOP 4 INC A 6 INC X 7 INC [expr] 4 INC [X+expr] 6 DEC A 7 DEC X 4 DEC [expr] 6 DEC [X+expr] 7 IORD expr 4 IOWR expr 6 POP A 7 POP X 4 PUSH A CY7C65013 CY7C65113 Function Page operand opcode cycles 20 4 acc direct 23 7 ...
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... AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 10 JACC 5 (or 4) INDEX 5 (or 4) CY7C65013 CY7C65113 operand opcode cycles direct 31 5 index 32 6 direct 33 7 index 34 8 direct 35 7 index 36 8 direct 37 7 index 38 8 ...
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... USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub interrupt vector 0x0014 Reserved 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF (8 KB -32) PROM ends here (CY7C65013, CY7C65113) CY7C65013 CY7C65113 Page ...
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... Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7). See Table 17-1. Document #: 38-08002 Rev. *B Address 0x00 Program Stack Growth user selected User variables USB FIFO space for up to two Addresses and five endpoints 0xFF CY7C65013 CY7C65113 Data Stack Growth Page [2] ...
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... Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register. 5.6 Address Modes The CY7C65013 and CY7C65113 microcontrollers support three addressing modes for instructions that require data operands:: data, direct, and indexed. 5.6.1 Data (Immediate) “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, consider the instruction that loads A with the constant 0xD8: • ...
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... Figure 6-1. Clock Oscillator On-Chip Circuit to stabilize at a valid operating voltage before the chip executes code. drops below approximately 2.5V, and remains asserted until V CC CY7C65013 CY7C65113 level is reached and that CC has risen above approximately 2.5V, and the CC rises above this level ...
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... This executes before any ISR ... ; Remaining code for exiting suspend routine. Document #: 38-08002 Rev WATCH No write to WDT register, so WDR goes HIGH Figure 7-1. Watchdog Reset (Address 0x26) CY7C65013 CY7C65113 of the last clear (see Section WATCH Execution begins at Reset Vector 0x0000 or Gnd. Note: CC Page ...
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... P1.5 P1.4 Reserved R/W R/W R Figure 9-3. Port1 Data P2.5 P2.4 P2.3 R/W R/W R Figure 9-4. Port 2 Data CY7C65013 CY7C65113 Q2 GPIO PIN sink sink Address 0x00 2 1 P0.2 P0.1 P0.0 R/W R/W R Address 0x01 2 1 P1.2 P1.1 P1.0 R/W R/W R/W ...
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... Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0] be written with a ‘0.’ When the CY7C65013 is used, the P1[3], P2[2:0], and P3[7:2] should be written with a ‘0.’ ...
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... Enable Figure 9-7. Port 0 Interrupt Enable P1.5 Intr P1.4 Intr Reserved Enable Enable Figure 9-8. Port 1 Interrupt Enable CY7C65013 CY7C65113 Interrupt Polarity 0 Disabled 1 – (Falling Edge) 0 Disabled 1 Disabled 0 Disabled 1 – (Falling Edge) 0 Disabled 1 + (Rising Edge) Address 0x04 P0.2 Intr P0.1 Intr P0 ...
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... Timer Bit 5 Timer Bit 4 Timer Bit Figure 10-1. Timer LSB Register Reserved Reserved Timer Bit 11 Timer Bit 10 – – Figure 10-2. Timer MSB Register CY7C65013 CY7C65113 Address 0x06 Reserved Reserved Reserved Address 0x07 Reserved P3.1 Intr P0.3 Intr Enable Enable ...
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... Figure 11- Configuration Register Port Width (Bit1, Figure 11- Data Register (Figure 12-1) and interrupt, as all bits are valid at that time. Polling this register at other times could CY7C65013 CY7C65113 1.024-ms interrupt 128- s interrupt MHz clock To Timer Registers C-compatible interface. I C-compatible function Port Width bit (Bit 1, Figure 11-1) select the ...
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... C-compatible block is busy with a transaction, 0 when transaction is complete. 2 C-compatible block to initiate a master mode transaction by sending a start bit and 2 C-compatible block performs any required arbitration and clock synchronization. IN the CY7C65013 CY7C65113 2 C SDA data is connected to bit Port Configuration Register (Section 2 C Status and Control Register (bit 0, ...
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... C-compatible mode, the two pins operate in open drain mode, independent USB Bus Power-on Suspend Reset Reset Interrupt R/W R/W R CY7C65013 CY7C65113 2 C Status and Control register. This 2 C start or restart. 2 C-compatible bus, 2 C-compatible pins. When this bit is cleared, Address 0xFF 2 1 Interrupt Reserved Run Enable Sense ...
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... Document #: 38-08002 Rev C-compatible operation, internal USB hub and USB traffic conditions GPIO Reserved USB Hub Interrupt Interrupt Enable Enable R Figure 14-1. Global Interrupt Enable Register CY7C65013 CY7C65113 Address 0X20 1.024-ms 128- s Interrupt Interrupt Enable Enable R/W R Page USB Bus ...
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... RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed. Document #: 38-08002 Rev Reserved EPB1 EPB0 Interrupt Interrupt Enable Enable – R/W R/W – CY7C65013 CY7C65113 Address 0X21 EPA2 EPA1 EPA0 Interrupt Interrupt Interrupt Enable Enable Enable R/W R/W R ...
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... USB Address B Endpoint 0 interrupt 0x0010 USB Address B Endpoint 1 interrupt 0x0012 USB Hub interrupt 0x0014 DAC interrupt 0x0016 GPIO interrupt 2 0x0018 I C interrupt CY7C65013 CY7C65113 To CPU CPU IRQ Sense IRQ Global Int Enable Interrupt Sense Enable Bit Controlled by DI, EI, and CLR RETI Instructions ...
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... GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read theGPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt logic is shown in Figure 14-4 Document #: 38-08002 Rev. *B CY7C65013 CY7C65113 (10 clock cycles for the CALL instruction) + Page ...
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... Figure 14-4. GPIO Interrupt Structure 2 C-compatible bus to signal the need for firmware interaction. This generally 2 C-compatible bus and leave the I2C-compatible hardware in the idle state. 2 C-compatible bus to generate the interrupt interrupt occurs. CY7C65013 CY7C65113 GPIO Interrupt Flip Flop Interrupt Priority Encoder CLR 2 C registers ...
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... USB address (for example, Address A). Document #: 38-08002 Rev. *B CY7C65013 CY7C65113 must be ext Page ...
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... R/W R/W R Figure 16-1. Hub Ports Connect Status 5 4 Port 6 Port 5 Port 4 Speed Speed Speed R/W R/W R Figure 16-2. Hub Ports Speed CY7C65013 CY7C65113 to indicate full speed USB device. REG Address 0x48 Port 3 Port 2 Connect Connect Status Status R/W R Address 0x4A 3 2 ...
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... This register is not reset by USB bus reset. These bits must be cleared before going into suspend. Document #: 38-08002 Rev Port 6 Port 5 Enable Enable Enable R/W R Figure 16-3. Hub Ports Enable Register may cause current flow into the pin. CY7C65013 CY7C65113 Port 4 Port 3 Port 2 Enable Enable R/W R/W R Address 0x49 ...
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... Figure 16-6. Hub Ports Force Low Register 5 4 Port 6 Port 5 Port 4 SE0 Status SE0 Status SE0 Status Figure 16-7. Hub Ports SE0 Status Register CY7C65013 CY7C65113 Address 0x4B Port 2 Port 1 Control Bit 0 Control Bit 1 R/W R Address 0x51 2 1 Force Low Force Low D– ...
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... Figure 16-8. Hub Ports Data Register Port 6 Port 5 Port 4 Selective Selective Selective Suspend Suspend Suspend R/W R/W R Figure 16-9. Hub Ports Suspend Register CY7C65013 CY7C65113 ADDRESS 0x50 Port 3 Diff. Port 2 Diff. Port 1 Diff. Data Data Data Address 0x4D Port 3 Port 2 ...
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... Document #: 38-08002 Rev Resume 6 Resume 5 Resume Figure 16-10. Hub Ports Resume Status Register D– Bus Activity Upstream Upstream Figure 16-11. USB Status and Control Register CY7C65013 CY7C65113 Address 0x4E Resume 3 Resume Address 0x1F Control Control Action Action Bit 2 Bit 1 R/W R/W ...
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... Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1). Document #: 38-08002 Rev Device Device Device Address Address Address Bit 5 Bit 4 Bit 3 R/W R/W R Figure 17-1. USB Device Address Registers CY7C65013 CY7C65113 Addresses 0x10(A) and 0x40( Device Device Address Address Bit 2 Bit 1 R/W R Page Device Address ...
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... EPA4 0xB0 8 EPA3 0xB8 8 EPA2 0xC0 32 EPA1 0xE0 32 EPA0 Endpoint 0 ACK OUT Received R/W R CY7C65013 CY7C65113 [0,1] [1,1] One USB Address Endpoints) Start Start Address Size Label Address 0xD8 8 EPA3 0xA8 0xE0 8 EPA4 0xB0 0xE8 8 EPA0 0xB8 0xF0 8 EPA1 0xC0 0xF8 ...
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... R/W R/W R Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit 3 R/W R/W R Figure 17-4. USB Endpoint Counter Registers CY7C65013 CY7C65113 [5] Addresses 0x14, 0x16, 0x44 Mode Bit 2 Mode Bit 1 R/W R Addresses 0x11, 0x13, 0x15, 0x41, 0x43 Byte Count Byte Count Bit 2 ...
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... For details on what conditions are required to generate an endpoint interrupt, refer to Table 18-2. 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. Document #: 38-08002 Rev. *B CY7C65013 CY7C65113 Page ...
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... C Data Packet UPDATE Host To Device Data 1/0 Data Packet SETUP Host To Device Data 1/0 Data Packet CY7C65013 CY7C65113 Host To Device Hand Shake Packet UPDATE Device To Host C S ACK NAK STAL 16 C Hand Shake UPDATE Packet UPDATE only if FIFO is written Page ...
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... Is set by SIE on an ACK from mode 1101 (Ack In) TX Count ignore On issuance of an ACK this mode is changed by SIE to 1100 (NAK In) stall ignore NAK check Is set by SIE on an ACK from mode 1111 (Ack In – Status Out) – Status Out) CY7C65013 CY7C65113 Comments Page ...
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... DVAL COUNT Setup Byte Count (bits 0..5, Figure 17-4) Data Valid (bit 6, Figure 17-4) Data0/1 (bit7 Figure 17-4) (Bit[7..5], Figure 17-2) The validity of the received data CY7C65013 CY7C65113 In Out ACK Response SIE’s Response to the Host PID Status Bits Endpoint Mode bits ...
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... Changes made by SIE to Internal Registers and Mode Bits dval DTOG DVAL COUNT Setup valid 1 1 updates UC valid 0 1 updates UC valid updates 1 updates invalid CY7C65013 CY7C65113 In Out ACK Mode Bits Response ACK NoChange ignore NoChange ignore In Out ACK Mode Bits Response NoChange ignore NoChange NAK 1 ...
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... UC invalid updates updates updates updates Changes made by SIE to Internal Registers and Mode Bits dval DTOG DVAL COUNT Setup CY7C65013 CY7C65113 NoChange ACK Stall Stall NoChange ignore NoChange ignore NoChange NAK NoChange ACK Stall Stall NoChange ignore NoChange ignore Stall In Out ACK ...
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... ACK Mode Bit 3 IN OUT Received Received Data Valid Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit ACK Mode Bit 3 CY7C65013 CY7C65113 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] P0.2 P0.1 P0.0 BBBBBBBB P1.2 P1.1 P1.0 BBBBBBBB P2.2 P2.1 P2.0 BBBBBBBB P3 ...
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... D–[3] D+[2] Reserved Force Low Force Low Force Low D+[7] D–[7] D+[6] Watchdog USB Bus Power-on Suspend Reset Reset Reset Interrupt CY7C65013 CY7C65113 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] Port 3 Port 2 Port 1 BBBBBBBB Connect Connect Connect Status Status Status Port 3 Port 2 ...
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... Vref OUT 2.2 uF . ext 22x8(R D0- D1- D0+ D1+ D2- XTALO D2+ D3- XTALI D3+ GND GND D4- Vpp D4+ 15K(x8) (R UDN POWER MANAGEMENT ..............................................................................................................–0.5V to +7.0V CY7C65013 CY7C65113 ) ext ) USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND + 0. 0.5V CC Page ...
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... General Purpose I/O (GPIO) All ports, low-to-high edge All ports, high-to-low edge 1.9 mA (all ports 0,1,2, 6.0 MHz) OSC Description Clock Source [10] USB Full-speed Signaling / below approximately 2.5V. CC CY7C65013 CY7C65113 Min. Max. Unit 3.15 3.45 V –0.4 0 0.2 V 0.8 2.5 V 0.8 2.0 V ...
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... Switching Characteristics t Full Speed Date Rate dratefs t Watchdog Timer Period watch CLOCK D D 24.0 Ordering Information Ordering Code PROM Size CY7C65013-PVC 8 KB CY7C65113- CY7C65013- CY7C65113- 25.0 Package Diagrams Document #: 38-08002 Rev 6.0 MHz) (continued) OSC Timer Signals t CYC 90% 90% 10% ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-lead (300-Mil) Molded DIP P21 48-lead (600-Mil) Molded DIP P25 28-lead (300-Mil) Molded SOIC S21 2 C system, provided that the system conforms to the I CY7C65013 CY7C65113 51-85014-*B 51-85020-*A 51-85026-* Standard Specification Page ...
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... Document History Page Document Title: CY7C65013/CY7C65113 USB Hub with Microcontroller Document Number: 38-08002 REV. ECN NO. Issue Date ** 109965 02/22/02 *A 120372 12/17/02 *B 124522 03/13/03 Document #: 38-08002 Rev. *B Orig. of Change SZV Change from Spec number: 38-00590 to 38-08002 MON Added register bit definitions. Added default bit state of each register. ...