CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 43

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

.
Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend)
Document #: 38-08002 Rev. *B
SETUP (if accepting SETUPs)
Properties of Incoming Packet
Mode Bits
See Table 18-1
See Table 18-1
See Table 18-1
Properties of Incoming Packet
Mode Bits
DISABLED
0
Nak In/Out
0
0
Ignore In/Out
0
0
Stall In/Out
0
0
CONTROL WRITE
Properties of Incoming Packet
Mode Bits
Normal Out/premature status In
1
1
1
1
NAK Out/premature status In
1
1
1
1
Status In/extra Out
0
0
0
0
CONTROL READ
Properties of Incoming Packet
Mode Bits
Normal In/premature status Out
1
1
1
1
1
1
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete. This represents about a 1- s window in which the CPU is locked
from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that
the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of
the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to
make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This
read will of course unlock the register. So care must be taken not to overwrite the register elsewhere
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
token
Setup
Setup
Setup
token
x
Out
In
Out
In
Out
In
token
Out
Out
Out
In
Out
Out
Out
In
Out
Out
Out
In
token
Out
Out
Out
Out
Out
In
count
<= 10
> 10
x
count
x
x
x
x
x
x
x
count
<= 10
> 10
x
x
<= 10
> 10
x
x
<= 10
> 10
x
x
count
2
2
!=2
> 10
x
x
buffer
data
junk
junk
buffer
UC
UC
UC
UC
UC
UC
UC
buffer
data
junk
junk
UC
UC
UC
UC
UC
UC
UC
UC
UC
buffer
UC
UC
UC
UC
UC
UC
dval
valid
x
invalid
dval
x
x
x
x
x
x
x
dval
valid
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
dval
valid
valid
valid
x
invalid
x
Changes made by SIE to Internal Registers and Mode Bits
DTOG
updates
updates
updates
Changes made by SIE to Internal Registers and Mode Bits
DTOG
UC
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
DTOG
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
DTOG
1
0
updates
UC
UC
UC
DVAL
1
updates
0
DVAL
UC
UC
UC
UC
UC
UC
UC
DVAL
1
updates
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
DVAL
1
1
1
UC
UC
UC
COUNT
updates
updates
updates
COUNT
UC
UC
UC
UC
UC
UC
UC
COUNT
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
COUNT
updates
updates
updates
UC
UC
UC
Setup
1
1
1
Setup
UC
UC
UC
UC
UC
UC
UC
Setup
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
Setup
UC
UC
UC
UC
UC
UC
In
UC
UC
UC
In
UC
UC
1
UC
UC
UC
1
In
UC
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
In
UC
UC
UC
UC
UC
1
Out
UC
UC
UC
Out
UC
1
UC
UC
UC
1
UC
Out
1
1
1
UC
1
UC
UC
UC
1
UC
UC
UC
Out
1
1
1
UC
UC
UC
ACK
1
UC
UC
ACK
UC
UC
UC
UC
UC
UC
UC
ACK
1
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
ACK
1
UC
UC
UC
UC
1
Mode Bits
0
NoChange
NoChange
Mode Bits
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
Mode Bits
1
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
0
NoChange
NoChange
NoChange
Mode Bits
NoChange
0
0
NoChange
NoChange
1
0 0 1 ACK
0 1 0 ACK
0 1 1 Stall
0 1 1 Stall
0 1 1 Stall
1 1 0 ACK (back)
CY7C65013
CY7C65113
Response
ignore
ignore
Response
ignore
NAK
NAK
ignore
ignore
Stall
Stall
Response
ignore
ignore
TX 0
NAK
ignore
ignore
TX 0
ignore
ignore
TX 0
Response
ACK
ignore
ignore
Page 43 of 51
Intr
yes
yes
yes
Intr
no
yes
yes
no
no
yes
yes
Intr
yes
yes
yes
yes
yes
no
no
yes
yes
no
no
yes
Intr
yes
yes
yes
no
no
yes