CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 27

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Table 14-1. Interrupt Vector Assignments
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
14.1
The Interrupt Vectors supported by the USB Controller are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
Document #: 38-08002 Rev. *B
AddrA ENP2 Int
USB Reset Int
Interrupt Vector Number
Interrupt Vectors
Not Applicable
I
2
C Int
1
1
1
10
11
12
1
2
3
4
5
6
7
8
9
CLK
D
D
CLK
CLK
D
CLR
CLR
CLR
Q
Q
Q
(Reg 0x21)
Figure 14-3. Interrupt Controller Function Diagram
Enable [2]
(Reg 0x20)
(Reg 0x20)
Enable [6]
Enable [0]
ROM Address
0x000C
0x000A
0x000E
0x0000
0x0002
0x0004
0x0006
0x0008
0x0010
0x0012
0x0014
0x0016
0x0018
USB Reset IRQ
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
AddrB EP0 IRQ
AddrB EP1 IRQ
128- s CLR
128- s IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
AddrA EP0 IRQ
AddrA EP1 CLR
AddrB EP0 CLR
AddrB EP1 CLR
Hub CLR
Hub IRQ
DAC CLR
DAC IRQ
GPIO CLR
GPIO IRQ
I
USB Reset Clear Interrupt
I
2
Interrupt Priority Encoder
2
C CLR
C IRQ
2
C interrupt) has the lowest priority.
Execution after Reset begins here
USB Bus Reset interrupt
128- s timer interrupt
1.024-ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
USB Address B Endpoint 0 interrupt
USB Address B Endpoint 1 interrupt
USB Hub interrupt
DAC interrupt
GPIO interrupt
I
2
C interrupt
IRQout
Vector
Acknowledge
To CPU
CPU
Interrupt
Interrupt
Enable
Global
Function
CLR
Bit
Controlled by DI, EI, and
RETI Instructions
CY7C65013
CY7C65113
IRQ Sense
Page 27 of 51
Int Enable
Sense
IRQ