CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 27

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Document #: 38-08002 Rev. *D
14.5
There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK on an IN transfer, or on the device ACK on an OUT transfer). If no ACK is received during
an IN transaction, no interrupt is generated.
14.6
A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by
the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port
Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive
the port (i.e., the port is being forced).
14.7
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the
GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt
logic is shown in Figure 14-4.
.
Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If
one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority
to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
14.8
The I
involves reading the I
I
subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I
to Section 12.0 for details on the I
When enabled, the I
bits are in the I
1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart
2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction
2
C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 13-1) to initiate the
GPIO
Pin
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next byte.
where the ACK bit was cleared to 0, no stop bit detection occurs.
IRA
2
C interrupt occurs after various events on the I
1 = Enable
0 = Disable
USB Endpoint Interrupts
USB Hub Interrupt
GPIO Interrupt
I
2
C Interrupt
2
C Status and Control Register.
2
C-compatible state machines generate interrupts on completion of the following conditions. The referenced
2
C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the
Port Interrupt
Enable Register
2
Configuration
C registers.
Register
M
U
X
Port
Figure 14-4. GPIO Interrupt Structure
1 = Enable
0 = Disable
2
C-compatible bus to signal the need for firmware interaction. This generally
(1 input per
OR Gate
GPIO pin)
(Bit 5, Register 0x20)
GPIO Interrupt
Global
Enable
1
GPIO Interrupt
Flip Flop
D
CLR
Q
Interrupt
Encoder
Priority
CY7C65113C
2
C registers. Refer
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Interrupt
IRQout
Vector